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Lorente Garcés, VJ.; Valero Bresó, A.; Sahuquillo Borrás, J.; Petit Martí, SV.; Canal, R.; López Rodríguez, PJ.; Duato Marín, JF. (2013). Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes. IEEE, ACM. https://doi.org/10.7873/DATE.2013.031
Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/75168
Título: | Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes | |
Autor: | Canal, Ramón Duato Marín, José Francisco | |
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Low-power modes in modern microprocessors rely
on low frequencies and low voltages to reduce the energy budget.
Nevertheless, manufacturing induced parameter variations can
make SRAM cells unreliable producing hard ...[+]
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Derechos de uso: | Reserva de todos los derechos | |
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Versión del editor: | http://dx.doi.org/10.7873/DATE.2013.031 | |
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This work was supported by the Spanish MICINN (TIN2010-18368) with the Consolider-Ingenio 2010 Programme co-funded by the European Commission FEDER funds (CSD2006-00046) and co-funded with the Plan E funds (TIN2009-14475-C04-01). ...[+]
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