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A Hardware Approach to Fairly Balance the Inter-Thread Interference in Shared Caches

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A Hardware Approach to Fairly Balance the Inter-Thread Interference in Shared Caches

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Selfa-Oliver, V.; Sahuquillo Borrás, J.; Petit Martí, SV.; Gómez Requena, ME. (2017). A Hardware Approach to Fairly Balance the Inter-Thread Interference in Shared Caches. IEEE Transactions on Parallel and Distributed Systems. 28(11):3021-3032. doi:10.1109/TPDS.2017.2713778

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/102495

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Title: A Hardware Approach to Fairly Balance the Inter-Thread Interference in Shared Caches
Author:
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Issued date:
Abstract:
[EN] Shared caches have become the common design choice in the vast majority of modern multi-core and many-core processors, since cache sharing improves throughput for a given silicon area. Sharing the cache, however, has ...[+]
Subjects: Cache partitioning , Multi-cores,fairness, Progress , Slowdown , Execution time in isolation
Copyrigths: Reserva de todos los derechos
Source:
IEEE Transactions on Parallel and Distributed Systems. (issn: 1045-9219 )
DOI: 10.1109/TPDS.2017.2713778
Publisher:
Institute of Electrical and Electronics Engineers
Publisher version: http://doi.org/10.1109/TPDS.2017.2713778
Thanks:
This work was supported in part by the Spanish Ministerio de Economia y Competitividad (MINECO) and Plan E funds, under grants TIN2014-62246-EXP and TIN2015-66972-C5-1-R.
Type: Artículo

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