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dc.contributor.author | Belloch Rodríguez, José Antonio![]() |
es_ES |
dc.contributor.author | Badia Contelles, J. M.![]() |
es_ES |
dc.contributor.author | Igual Peña, Francisco Daniel![]() |
es_ES |
dc.contributor.author | Gonzalez, Alberto![]() |
es_ES |
dc.contributor.author | Quintana Ortí, Enrique Salvador![]() |
es_ES |
dc.date.accessioned | 2020-04-28T06:02:23Z | |
dc.date.available | 2020-04-28T06:02:23Z | |
dc.date.issued | 2017-11 | es_ES |
dc.identifier.issn | 1549-8328 | es_ES |
dc.identifier.uri | http://hdl.handle.net/10251/141650 | |
dc.description.abstract | [EN] Numerous signal processing applications are emerging on both mobile and high-performance computing systems. These applications are subject to responsiveness constraints for user interactivity and, at the same time, must be optimized for energy efficiency. The increasingly heterogeneous power-versus-performance profile of modern hardware introduces new opportunities for energy savings as well as challenges. In this line, recent systems-on-chip (SoC) composed of low-power multicore processors, combined with a small graphics accelerator (or GPU), yield a notable increment of the computational capacity while partially retaining the appealing low power consumption of embedded systems. This paper analyzes the potential of these new hardware systems to accelerate applications that involve a large number of floating-point arithmetic operations mainly in the form of convolutions. To assess the performance, a headphone-based spatial audio application for mobile devices based on a Samsung Exynos 5422 SoC has been developed. We discuss different implementations and analyze the tradeoffs between performance and energy efficiency for different scenarios and configurations. Our experimental results reveal that we can extend the battery lifetime of a device featuring such an architecture by a 238% by properly configuring and leveraging the computational resources. | es_ES |
dc.description.sponsorship | This work was supported by the Spanish Ministerio de Economia y Competitividad projects under Grant TIN2014-53495-R and Grant TEC2015-67387-C4-1-R, in part by the University Project UJI-B2016-20, in part by the Project PROMETEOII/2014/003. The work of J. A. Belloch was supported by the GVA Post-Doctoral Contract under Grant APOSTD/2016/069. This paper was recommended by Associate Editor Y. Ha. | es_ES |
dc.language | Inglés | es_ES |
dc.publisher | Institute of Electrical and Electronics Engineers | es_ES |
dc.relation.ispartof | IEEE Transactions on Circuits and Systems I Regular Papers | es_ES |
dc.rights | Reserva de todos los derechos | es_ES |
dc.subject | Audio systems | es_ES |
dc.subject | Signal synthesis | es_ES |
dc.subject | Parallel architectures | es_ES |
dc.subject | Parallel processing | es_ES |
dc.subject | Heterogeneous (hybrid) systems | es_ES |
dc.subject | Performance and energy efficiency | es_ES |
dc.subject.classification | CIENCIAS DE LA COMPUTACION E INTELIGENCIA ARTIFICIAL | es_ES |
dc.subject.classification | TEORIA DE LA SEÑAL Y COMUNICACIONES | es_ES |
dc.subject.classification | ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES | es_ES |
dc.title | Optimized Fundamental Signal Processing Operations for Energy Minimization on Heterogeneous Mobile Devices | es_ES |
dc.type | Artículo | es_ES |
dc.identifier.doi | 10.1109/TCSI.2017.2761909 | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/MINECO//TIN2014-53495-R/ES/COMPUTACION HETEROGENEA DE BAJO CONSUMO/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/GVA//APOSTD%2F2016%2F069/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/UJI//UJI-B2016-20/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/GVA//PROMETEOII%2F2014%2F003/ES/Computación y comunicaciones de altas prestaciones y aplicaciones en ingeniería/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/MINECO//TEC2015-67387-C4-1-R/ES/SMART SOUND PROCESSING FOR THE DIGITAL LIVING/ | es_ES |
dc.rights.accessRights | Abierto | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Comunicaciones - Departament de Comunicacions | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Instituto Universitario de Telecomunicación y Aplicaciones Multimedia - Institut Universitari de Telecomunicacions i Aplicacions Multimèdia | es_ES |
dc.description.bibliographicCitation | Belloch Rodríguez, JA.; Badia Contelles, JM.; Igual Peña, FD.; Gonzalez, A.; Quintana Ortí, ES. (2017). Optimized Fundamental Signal Processing Operations for Energy Minimization on Heterogeneous Mobile Devices. IEEE Transactions on Circuits and Systems I Regular Papers. 65(5):1614-1627. https://doi.org/10.1109/TCSI.2017.2761909 | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.publisherversion | https://doi.org/10.1109/TCSI.2017.2761909 | es_ES |
dc.description.upvformatpinicio | 1614 | es_ES |
dc.description.upvformatpfin | 1627 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.description.volume | 65 | es_ES |
dc.description.issue | 5 | es_ES |
dc.relation.pasarela | S\354062 | es_ES |
dc.contributor.funder | Universitat Jaume I | es_ES |
dc.contributor.funder | Generalitat Valenciana | es_ES |
dc.contributor.funder | Ministerio de Economía y Competitividad | es_ES |
dc.contributor.funder | Ministerio de Economía, Industria y Competitividad | es_ES |