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dc.contributor.author | Catalán, Sandra | es_ES |
dc.contributor.author | Herrero, José R. | es_ES |
dc.contributor.author | Quintana Ortí, Enrique Salvador | es_ES |
dc.contributor.author | Rodríguez-Sánchez, Rafael | es_ES |
dc.date.accessioned | 2020-09-12T03:34:57Z | |
dc.date.available | 2020-09-12T03:34:57Z | |
dc.date.issued | 2018-08 | es_ES |
dc.identifier.issn | 0167-8191 | es_ES |
dc.identifier.uri | http://hdl.handle.net/10251/149951 | |
dc.description.abstract | [EN] We analyze the benefits of look-ahead in the parallel execution of the LU factorization with partial pivoting (LUpp) in two distinct "asymmetric" multicore scenarios. The first one corresponds to an actual hardware-asymmetric architecture such as the Samsung Exynos 5422 system-on-chip (SoC), equipped with an ARM big.LITTLE processor consisting of a quad core Cortex-A15 cluster plus a quad-core Cortex-A7 cluster. For this scenario, we propose a careful mapping of the different types of tasks appearing in LUpp to the computational resources, in order to produce an efficient architecture-aware exploitation of the computational resources integrated in this SoC. The second asymmetric configuration appears in a hardware-symmetric multicore architecture where the cores can individually operate at a different frequency levels. In this scenario, we show how to employ the frequency slack to accelerate the tasks in the critical path of LUpp in order to produce a faster global execution as well as a lower energy consumption. (C) 2018 Elsevier B.V. All rights reserved. | es_ES |
dc.description.sponsorship | The researchers from Universidad Jaume I were supported by projects TIN2014-53495-R and TIN2017-82972-R of MINECO and FEDER, and the FPU program of MECD. The researcher from Universitat Politecnica de Catalunya was supported by projects TIN2015-65316-P of MINECO and FEDER and 2017-SGR-1414 from the Generalitat de Catalunya. | es_ES |
dc.language | Inglés | es_ES |
dc.publisher | Elsevier | es_ES |
dc.relation.ispartof | Parallel Computing | es_ES |
dc.rights | Reconocimiento - No comercial - Sin obra derivada (by-nc-nd) | es_ES |
dc.subject | Dense linear algebra | es_ES |
dc.subject | LU factorization | es_ES |
dc.subject | Look-ahead | es_ES |
dc.subject | Asymmetric multicore processors | es_ES |
dc.subject | Multi-threading | es_ES |
dc.subject | Frequency scaling | es_ES |
dc.subject.classification | ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES | es_ES |
dc.title | Static scheduling of the LU factorization with look-ahead on asymmetric multicore processors | es_ES |
dc.type | Artículo | es_ES |
dc.identifier.doi | 10.1016/j.parco.2018.04.006 | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/MINECO//TIN2014-53495-R/ES/COMPUTACION HETEROGENEA DE BAJO CONSUMO/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2013-2016/TIN2017-82972-R/ES/TECNICAS ALGORITMICAS PARA COMPUTACION DE ALTO RENDIMIENTO CONSCIENTE DEL CONSUMO ENERGETICO Y RESISTENTE A ERRORES/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/Generalitat de Catalunya//2017 SGR 1414/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/MINECO//TIN2015-65316-P/ES/COMPUTACION DE ALTAS PRESTACIONES VII/ | es_ES |
dc.rights.accessRights | Abierto | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors | es_ES |
dc.description.bibliographicCitation | Catalán, S.; Herrero, JR.; Quintana Ortí, ES.; Rodríguez-Sánchez, R. (2018). Static scheduling of the LU factorization with look-ahead on asymmetric multicore processors. Parallel Computing. 76:18-27. https://doi.org/10.1016/j.parco.2018.04.006 | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.publisherversion | https://doi.org/ 10.1016/j.parco.2018.04.006 | es_ES |
dc.description.upvformatpinicio | 18 | es_ES |
dc.description.upvformatpfin | 27 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.description.volume | 76 | es_ES |
dc.relation.pasarela | S\381011 | es_ES |
dc.contributor.funder | Generalitat de Catalunya | es_ES |
dc.contributor.funder | European Regional Development Fund | es_ES |
dc.contributor.funder | Ministerio de Economía y Competitividad | es_ES |
dc.contributor.funder | Ministerio de Educación, Cultura y Deporte | es_ES |
dc.contributor.funder | Agencia Estatal de Investigación | es_ES |