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POWAR: Power-Aware Routing in HPC Networks with On/Off Links

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POWAR: Power-Aware Routing in HPC Networks with On/Off Links

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dc.contributor.author Andújar-Muñoz, Francisco José es_ES
dc.contributor.author Coll, Salvador es_ES
dc.contributor.author Alonso Díaz, Marina es_ES
dc.contributor.author López Rodríguez, Pedro Juan es_ES
dc.contributor.author Martínez-Rubio, Juan-Miguel es_ES
dc.date.accessioned 2020-10-05T07:00:00Z
dc.date.available 2020-10-05T07:00:00Z
dc.date.issued 2019-01 es_ES
dc.identifier.issn 1544-3566 es_ES
dc.identifier.uri http://hdl.handle.net/10251/151096
dc.description.abstract [EN] In order to save energy in HPC interconnection networks, one usual proposal is to switch idle links into a low-power mode after a certain time without any transmission, as IEEE Energy Efficient Ethernet standard proposes. Extending the low-power mode mechanism, we propose POWer-Aware Routing (POWAR), a simple power-aware routing and selection function for fat-tree and torus networks. POWAR adapts the amount of network links that can be used, taking into account the network load, and obtaining great energy savings in the network (55%-65%) and the entire system (9%-10%) with negligible performance overhead. es_ES
dc.description.sponsorship This work has been supported by the Spanish MINECO and European Commission (FEDER funds) under project TIN2015-66972-C5-1-R. Francisco J. Andujar has been partially funded by the Spanish MICINN and by the ERDF program of the European Union: PCAS Project (TIN2017-88614-R), CAPAP-H6 (TIN2016-81840-REDT), and Junta de Castilla y Leon FEDER Grant VA082P17 (PROPHET Project). es_ES
dc.language Inglés es_ES
dc.publisher Association for Computing Machinery es_ES
dc.relation.ispartof ACM Transactions on Architecture and Code Optimization es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject Switch architecture es_ES
dc.subject High-performance computing es_ES
dc.subject Interconnection networks es_ES
dc.subject Power saving es_ES
dc.subject Routing algorithms es_ES
dc.subject.classification TECNOLOGIA ELECTRONICA es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.title POWAR: Power-Aware Routing in HPC Networks with On/Off Links es_ES
dc.type Artículo es_ES
dc.identifier.doi 10.1145/3293445 es_ES
dc.relation.projectID info:eu-repo/grantAgreement/MINECO//TIN2015-66972-C5-1-R/ES/TECNICAS PARA LA MEJORA DE LAS PRESTACIONES, COSTE Y CONSUMO DE ENERGIA DE LOS SERVIDORES/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2013-2016/TIN2017-88614-R/ES/ESPACIO DE DIRECCIONES PARTICIONADO, COMUNICADO Y ESCALABLE EN ENTORNOS HETEROGENEOS/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/MINECO//TIN2016-81840-REDT/ES/RED DE COMPUTACION DE ALTAS PRESTACIONES EN ARQUITECTURAS HETEROGENEAS (CAPAP-H6)/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/Junta de Castilla y León//VA082P17/ES/PROPHET: Paralelización de algoritmos secuenciales de aplicaciones científicas y de ingeniería desplegables en plataformas heterogéneas interconectadas/ es_ES
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica es_ES
dc.description.bibliographicCitation Andújar-Muñoz, FJ.; Coll, S.; Alonso Díaz, M.; López Rodríguez, PJ.; Martínez-Rubio, J. (2019). POWAR: Power-Aware Routing in HPC Networks with On/Off Links. ACM Transactions on Architecture and Code Optimization. 15(4):1-22. https://doi.org/10.1145/3293445 es_ES
dc.description.accrualMethod S es_ES
dc.relation.publisherversion https://doi.org/10.1145/3293445 es_ES
dc.description.upvformatpinicio 1 es_ES
dc.description.upvformatpfin 22 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 15 es_ES
dc.description.issue 4 es_ES
dc.relation.pasarela S\394924 es_ES
dc.contributor.funder Junta de Castilla y León es_ES
dc.contributor.funder European Regional Development Fund es_ES
dc.contributor.funder Ministerio de Economía y Competitividad es_ES
dc.contributor.funder Agencia Estatal de Investigación es_ES
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