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On Microarchitectural Mechanisms for Cache Wearout Reduction

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On Microarchitectural Mechanisms for Cache Wearout Reduction

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Valero Bresó, A.; Miralaei, N.; Petit Martí, SV.; Sahuquillo Borrás, J.; Jones, TM. (2017). On Microarchitectural Mechanisms for Cache Wearout Reduction. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25(3):857-871. https://doi.org/10.1109/TVLSI.2016.2625809

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/152477

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Title: On Microarchitectural Mechanisms for Cache Wearout Reduction
Author: Valero Bresó, Alejandro Miralaei, Negar Petit Martí, Salvador Vicente Sahuquillo Borrás, Julio Jones, Timothy M.
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Issued date:
Abstract:
[EN] Hot carrier injection (HCI) and bias temperature instability (BTI) are two of the main deleterious effects that increase a transistor's threshold voltage over the lifetime of a microprocessor. This voltage degradation ...[+]
Subjects: Bias temperature instability (BTI) , Cache memories , Cell flips , Duty cycle distribution , Hot carrier injection (HCI) , Threshold voltage degradation
Copyrigths: Reserva de todos los derechos
Source:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. (issn: 1063-8210 )
DOI: 10.1109/TVLSI.2016.2625809
Publisher:
Institute of Electrical and Electronics Engineers
Publisher version: https://doi.org/10.1109/TVLSI.2016.2625809
Project ID:
info:eu-repo/grantAgreement/EC/FP7/287759/EU
EPSRC/EP/K026399/1
EPSRC/EP/J016284/1
MINISTERIO DE ECONOMIA Y EMPRESA/TIN2015-66972-C5-1-R
Thanks:
This work was supported in part by the Spanish Ministerio de Economia y Competitividad within the Plan E Funds under Grant TIN2015-66972-C5-1-R, in part by the HiPEAC Collaboration Grant funded by the FP7 HiPEAC Network ...[+]
Type: Artículo

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