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Precise Runahead Execution

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Precise Runahead Execution

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dc.contributor.author Naithani, Ajeya es_ES
dc.contributor.author Feliu-Pérez, Josué es_ES
dc.contributor.author Adileh, Almutaz es_ES
dc.contributor.author Eeckhout, Lieven es_ES
dc.date.accessioned 2020-12-15T04:32:09Z
dc.date.available 2020-12-15T04:32:09Z
dc.date.issued 2019-06 es_ES
dc.identifier.issn 1556-6056 es_ES
dc.identifier.uri http://hdl.handle.net/10251/157199
dc.description © 2019 IEEE. Personal use of this material is permitted. Permissíon from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertisíng or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. es_ES
dc.description.abstract [EN] Runahead execution improves processor performance by accurately prefetching long-latency memory accesses. When a long-latency load causes the instruction window to fill up and halt the pipeline, the processor enters runahead mode and keeps speculatively executing code to trigger accurate prefetches. A recent improvement tracks the chain of instructions that leads to the long-latency load, stores it in a runahead buffer, and executes only this chain during runahead execution, with the purpose of generating more prefetch requests during runahead execution. Unfortunately, all these prior runahead proposals have shortcomings that limit performance and energy efficiency because they discard the full instruction window to enter runahead mode and then flush the pipeline to restart normal operation. This significantly constrains the performance benefits and increases the energy overhead of runahead execution. In addition, runahead buffer limits prefetch coverage by tracking only a single chain of instructions that lead to the same long-latency load. We propose precise runahead execution (PRE) to mitigate the shortcomings of prior work. PRE leverages the renaming unit to track all the dependency chains leading to long-latency loads. PRE uses a novel approach to manage free processor resources to execute the detected instruction chains in runahead mode without flushing the pipeline. Our results show that PRE achieves an additional 21.1 percent performance improvement over the recent runahead proposals while reducing energy consumption by 6.1 percent. es_ES
dc.description.sponsorship This research is supported through FWO grants no. G.0434.16N and G.0144.17N, and European Research Council (ERC) Advanced Grant agreement no. 741097. es_ES
dc.language Inglés es_ES
dc.publisher Institute of Electrical and Electronics Engineers es_ES
dc.relation.ispartof IEEE Computer Architecture Letters es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject Microarchitecture es_ES
dc.subject Single-core performance es_ES
dc.subject Runahead execution es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.title Precise Runahead Execution es_ES
dc.type Artículo es_ES
dc.identifier.doi 10.1109/LCA.2019.2910518 es_ES
dc.relation.projectID info:eu-repo/grantAgreement/EC/H2020/741097/EU/Load Slice Core: A Power and Cost-Efficient Microarchitecture for the Future/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/FWO//G.0434.16N/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/FWO//G.0144.17N/ es_ES
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.description.bibliographicCitation Naithani, A.; Feliu-Pérez, J.; Adileh, A.; Eeckhout, L. (2019). Precise Runahead Execution. IEEE Computer Architecture Letters. 18(1):71-74. https://doi.org/10.1109/LCA.2019.2910518 es_ES
dc.description.accrualMethod S es_ES
dc.relation.publisherversion https://doi.org/10.1109/LCA.2019.2910518 es_ES
dc.description.upvformatpinicio 71 es_ES
dc.description.upvformatpfin 74 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 18 es_ES
dc.description.issue 1 es_ES
dc.relation.pasarela S\386785 es_ES
dc.contributor.funder Research Foundation Flanders es_ES


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