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Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM

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Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM

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dc.contributor.author Baraza Calvo, Juan Carlos es_ES
dc.contributor.author Gracia-Morán, Joaquín es_ES
dc.contributor.author Saiz-Adalid, Luis-J. es_ES
dc.contributor.author Gil Tomás, Daniel Antonio es_ES
dc.contributor.author Gil, Pedro es_ES
dc.date.accessioned 2021-04-29T03:32:13Z
dc.date.available 2021-04-29T03:32:13Z
dc.date.issued 2020-12 es_ES
dc.identifier.uri http://hdl.handle.net/10251/165770
dc.description.abstract [EN] Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault tolerance mechanism based on error correction codes (ECC), able to modify its behavior when the error conditions change without increasing the redundancy. As a case example, we have designed a mechanism that can detect intermittent faults and swap from an initial generic ECC to a specific ECC capable of tolerating one intermittent fault. We have inserted the mechanism in the memory system of a 32-bit RISC processor and validated it by using VHDL simulation-based fault injection. We have used two (39, 32) codes: a single error correction-double error detection (SEC-DED) and a code developed by our research group, called EPB3932, capable of correcting single errors and double and triple adjacent errors that include a bit previously tagged as error-prone. The results of injecting transient, intermittent, and combinations of intermittent and transient faults show that the proposed mechanism works properly. As an example, the percentage of failures and latent errors is 0% when injecting a triple adjacent fault after an intermittent stuck-at fault. We have synthesized the adaptive fault tolerance mechanism proposed in two types of FPGAs: non-reconfigurable and partially reconfigurable. In both cases, the overhead introduced is affordable in terms of hardware, time and power consumption. es_ES
dc.description.sponsorship This research was supported in part by the Spanish Government, project TIN2016-81,075-R, and by Primeros Proyectos de Investigacion (PAID-06-18), Vicerrectorado de Investigacion, Innovacion y Transferencia de la Universitat Politecnica de Valencia (UPV), project 20190032. es_ES
dc.language Inglés es_ES
dc.publisher MDPI AG es_ES
dc.relation.ispartof Electronics es_ES
dc.rights Reconocimiento (by) es_ES
dc.subject Fault tolerance es_ES
dc.subject Error control codes es_ES
dc.subject Fault injection es_ES
dc.subject Hardware description languages es_ES
dc.subject Logic circuits es_ES
dc.subject FPGA es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.title Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM es_ES
dc.type Artículo es_ES
dc.identifier.doi 10.3390/electronics9122074 es_ES
dc.relation.projectID info:eu-repo/grantAgreement/UPV//PAID-06-18/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/UPV//20190032/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/MINECO//TIN2016-81075-R/ES/MECANISMOS DE ADAPTACION CONFIABLE PARA VEHICULOS AUTONOMOS Y CONECTADOS/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/UPV//SP20180334/ es_ES
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.description.bibliographicCitation Baraza Calvo, JC.; Gracia-Morán, J.; Saiz-Adalid, L.; Gil Tomás, DA.; Gil, P. (2020). Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM. Electronics. 9(12):1-30. https://doi.org/10.3390/electronics9122074 es_ES
dc.description.accrualMethod S es_ES
dc.relation.publisherversion https://doi.org/10.3390/electronics9122074 es_ES
dc.description.upvformatpinicio 1 es_ES
dc.description.upvformatpfin 30 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 9 es_ES
dc.description.issue 12 es_ES
dc.identifier.eissn 2079-9292 es_ES
dc.relation.pasarela S\423083 es_ES
dc.contributor.funder Universitat Politècnica de València es_ES
dc.contributor.funder Ministerio de Economía y Competitividad es_ES
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