Navarro, M.; Pons-Escat, L.; Sahuquillo Borrás, J. (2021). Hy-Sched: A Simple Hyperthreading-Aware Thread to Core Allocation Strategy. IEEE Computer Architecture Letters. 20(1):26-29. https://doi.org/10.1109/LCA.2021.3051393
Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/184798
Título:
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Hy-Sched: A Simple Hyperthreading-Aware Thread to Core Allocation Strategy
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Autor:
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Navarro, Marta
Pons-Escat, Lucía
Sahuquillo Borrás, Julio
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Entidad UPV:
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Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
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Fecha difusión:
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Resumen:
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[EN] Simultaneous multithreading processors are dominating the High Computing Performance market. Among these processors, those supporting only two threads are being the most widely deployed in current systems, thus, only ...[+]
[EN] Simultaneous multithreading processors are dominating the High Computing Performance market. Among these processors, those supporting only two threads are being the most widely deployed in current systems, thus, only two threads compete at run-time for intra-core resources. The performance of these processors can be boosted by selecting symbiotic applications to be executed on the same core, which reduces the inter-application interference considerably. In this letter we propose Hy-Sched, an scheduling algorithm that exploits symbiosis to make pairs of applications to be launched on the same physical core. The proposed approach lies on the categories of the Top-Down Method for Performance Analysis. Different variants of the algorithm are explored. Experimental results show that Hy-Sched outperforms Linux on average by 15 percent in the studied workloads.
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Palabras clave:
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Symbiosis
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Benchmark testing
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Mathematical model
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Interference
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Instruction sets
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Linux
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Hardware
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Simultaneous multithreading
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Symbiotic applications
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Intra-core interference
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Derechos de uso:
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Reserva de todos los derechos
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Fuente:
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IEEE Computer Architecture Letters. (issn:
1556-6056
)
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DOI:
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10.1109/LCA.2021.3051393
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Editorial:
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Institute of Electrical and Electronics Engineers
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Versión del editor:
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https://doi.org/10.1109/LCA.2021.3051393
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Código del Proyecto:
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info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/RTI2018-098156-B-C51/ES/TECNOLOGIAS INNOVADORAS DE PROCESADORES, ACELERADORES Y REDES, PARA CENTROS DE DATOS Y COMPUTACION DE ALTAS PRESTACIONES/
info:eu-repo/grantAgreement/GVA//AICO%2F2019%2F317//REDUCCIO DEL TEMPS D,EXECUCIO DE LES APLICACIONS ACTUANT SOBRE TECNOLOGIES INNOVADORES/
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Descripción:
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© 2021 IEEE. Personal use of this material is permitted. Permissíon from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertisíng or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
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Agradecimientos:
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This work was supported in part by Ministerio de Ciencia, Innovacion y Universidades and the European ERDF under Grant RTI2018-098156-B-C51, and Generalitat Valenciana under Grant AICO/2019/317.
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Tipo:
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Artículo
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