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Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes

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Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes

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dc.contributor.author Valls Coquillat, Javier es_ES
dc.contributor.author García-Herrero, Francisco es_ES
dc.contributor.author Raveendran, Nithin es_ES
dc.contributor.author Vasic, Bane es_ES
dc.date.accessioned 2022-10-10T18:08:07Z
dc.date.available 2022-10-10T18:08:07Z
dc.date.issued 2021 es_ES
dc.identifier.uri http://hdl.handle.net/10251/187403
dc.description.abstract [EN] Quantum processors need to improve their reliability to scale up the number of qubits and increase the number of algorithms that can execute. To reduce the logical error rate of the quantum systems, the use of error correction codes and decoders has been established as a low-cost and feasible approach, with good results from a theoretical perspective, for mid and long-term architectures. While most of the authors are focused on the algorithms to improve the correction capability of quantum computers, without taking into account a fundamental implementation aspect for their deployment in a real system, i.e., their latency must be bounded to avoid the qubit decoherence, only a few propose hardware architectures and they just include time estimations of their decoding latency. However, a real implementation has not been shown yet. In this work, we analyze from the point of view of hardware implementation two algorithmic options based on quantum low-density parity-check (QLDPC) codes: a) belief propagation min-sum decoders combined with codes with good error-floor behavior and b) belief propagation min-sum decoders concatenated with ordered statistics decoders (OSDs) for codes with early error-floor. The bounds for the maximum clock frequency required by the decoders to decode within the qubit coherence time are established as a parameter to show if a practical implementation is possible with the present or near future FPGA technology. Furthermore, real implementation results for a Xilinx FPGA device are provided, showing that some solutions can meet the timing constraints set up by the state-of-the-art quantum processors. es_ES
dc.description.sponsorship The work of Bane Vasi cent was supported by NSF under Grant CCF-1855879, GrantCCSS-2027844, GrantCCSS-2052751, and Grant NS-FERC 1941583. es_ES
dc.language Inglés es_ES
dc.publisher Institute of Electrical and Electronics Engineers es_ES
dc.relation.ispartof IEEE Access es_ES
dc.rights Reconocimiento (by) es_ES
dc.subject Decoding es_ES
dc.subject Codes es_ES
dc.subject Qubit es_ES
dc.subject Program processors es_ES
dc.subject Hardware es_ES
dc.subject Error correction codes es_ES
dc.subject Error correction es_ES
dc.subject Quantum error correction es_ES
dc.subject Syndrome based decoding es_ES
dc.subject Ordered statistics es_ES
dc.subject FPGA devices es_ES
dc.subject.classification TECNOLOGIA ELECTRONICA es_ES
dc.title Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes es_ES
dc.type Artículo es_ES
dc.identifier.doi 10.1109/ACCESS.2021.3118544 es_ES
dc.relation.projectID info:eu-repo/grantAgreement/NSF//CCF-1855879/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/NSF//CCSS-2027844/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/NSF//CCSS-2052751/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/NSF//NS-FERC 1941583/ es_ES
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica es_ES
dc.description.bibliographicCitation Valls Coquillat, J.; García-Herrero, F.; Raveendran, N.; Vasic, B. (2021). Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes. IEEE Access. 9:138734-138743. https://doi.org/10.1109/ACCESS.2021.3118544 es_ES
dc.description.accrualMethod S es_ES
dc.relation.publisherversion https://doi.org/10.1109/ACCESS.2021.3118544 es_ES
dc.description.upvformatpinicio 138734 es_ES
dc.description.upvformatpfin 138743 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 9 es_ES
dc.identifier.eissn 2169-3536 es_ES
dc.relation.pasarela S\448216 es_ES
dc.contributor.funder National Science Foundation, EEUU es_ES
dc.contributor.funder Universitat Politècnica de València es_ES
upv.costeAPC 1936 es_ES


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