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Reconfigurable Architecture of UFMC Transmitter for 5G and Its FPGA Prototype

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Reconfigurable Architecture of UFMC Transmitter for 5G and Its FPGA Prototype

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dc.contributor.author Kumar, Vikas es_ES
dc.contributor.author Mukherjee, Mithun es_ES
dc.contributor.author Lloret, Jaime es_ES
dc.date.accessioned 2022-10-13T18:07:19Z
dc.date.available 2022-10-13T18:07:19Z
dc.date.issued 2020-03 es_ES
dc.identifier.issn 1932-8184 es_ES
dc.identifier.uri http://hdl.handle.net/10251/187689
dc.description.abstract [EN] A universal-filtered multicarrier (UFMC) system that is a generalization of filtered orthogonal frequency-division multiplexing (OFDM) and filter-bank-based multicarrier is being considered as a potential candidate for fifth-generation due to its robustness against intercarrier interference as in cyclic-prefix-based OFDM systems. However, real-time hardware realization of multicarrier systems is limited by a large number of arithmetic units for inverse fast Fourier transform and pulse-shaping filters. In this paper, we aim to propose a low-complexity and reconfigurable architecture for a baseband UFMC transmitter. To the best of our knowledge, the proposed architecture is the first reconfigurable architecture that has the flexibility to choose the number of subcarriers in a subband without any change in hardware resources. In addition, the proposed architecture selects the filter from a group of filters with a single selection line. Moreover, we use a commercially available field-programmable gate array device for real-time testing and analyzing the baseband UFMC signal. From the extensive experiments, we study the occupied bandwidth, main-lobe power, and sidelobe power of the baseband signal with different filters in real-time scenarios. Finally, we measure the quantization error in baseband signal generation for the proposed UFMC transmitter architecture and find comparable with the error bound. es_ES
dc.language Inglés es_ES
dc.publisher Institute of Electrical and Electronics Engineers es_ES
dc.relation.ispartof IEEE Systems Journal es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject Error analysis es_ES
dc.subject Pulse-shaping filters es_ES
dc.subject Reconfigurable architectures es_ES
dc.subject Universal-filtered multicarrier (UFMC) es_ES
dc.subject.classification INGENIERIA TELEMATICA es_ES
dc.title Reconfigurable Architecture of UFMC Transmitter for 5G and Its FPGA Prototype es_ES
dc.type Artículo es_ES
dc.identifier.doi 10.1109/JSYST.2019.2923549 es_ES
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Comunicaciones - Departament de Comunicacions es_ES
dc.description.bibliographicCitation Kumar, V.; Mukherjee, M.; Lloret, J. (2020). Reconfigurable Architecture of UFMC Transmitter for 5G and Its FPGA Prototype. IEEE Systems Journal. 14(1):28-38. https://doi.org/10.1109/JSYST.2019.2923549 es_ES
dc.description.accrualMethod S es_ES
dc.relation.publisherversion https://doi.org/10.1109/JSYST.2019.2923549 es_ES
dc.description.upvformatpinicio 28 es_ES
dc.description.upvformatpfin 38 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 14 es_ES
dc.description.issue 1 es_ES
dc.relation.pasarela S\473091 es_ES


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