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dc.contributor.author | Tuzov, Ilya | es_ES |
dc.contributor.author | de-Andrés-Martínez, David | es_ES |
dc.contributor.author | Ruiz, Juan Carlos | es_ES |
dc.date.accessioned | 2023-05-30T06:16:42Z | |
dc.date.available | 2023-05-30T06:16:42Z | |
dc.date.issued | 2022-09-15 | es_ES |
dc.identifier.isbn | 978-1-6654-7402-3 | es_ES |
dc.identifier.uri | http://hdl.handle.net/10251/193734 | |
dc.description.abstract | [EN] Although initially considered for fast system prototyping, Field Programmable Gate Arrays (FPGAs) are gaining interest for implementing final products thanks to their inherent reconfiguration capabilities. As they are susceptible to soft errors in their configuration memory, the dependability of FPGA-based designs must be accurately evaluated to be used in critical systems. In recent years, research has focused on speeding up fault injection in FPGA-based systems by parallelising experimentation, reducing the injection time, and decreasing the number of experiments. Going a step further requires delving into the FPGA architecture, i.e. precisely determining which components are implementing the considered design (mapping) and which are exercised by the considered workload (profiling). After that, fault injection campaigns can focus on those components actually used to identify critical ones, i.e. those leading the target system to fail. Some manufacturers, like Xilinx, identify those bits in the FPGA configuration memory that may change the implemented design when affected by a soft error. However, their correspondence to particular components of the FPGA fabric and their relationship with the implementation-level model are yet unknown. This paper addresses whether the effort of reversing an FPGA architecture to filter out redundant and unused essential bits pays in terms of experimental time. Since the work of reversing the complete architecture of an FPGA is titanic, as the first step towards this ambitious goal, this paper focuses on those elements in charge of implementing the combinational logic of the design (Look-Up Tables). The experimental results that support this study derive from implementing three soft-core processors on a Zynq SoC FPGA and show the interest of the proposal. | es_ES |
dc.description.sponsorship | Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033. | es_ES |
dc.language | Inglés | es_ES |
dc.publisher | IEEE | es_ES |
dc.relation.ispartof | Proceedings of the 2022 18th European Dependable Computing Conference | es_ES |
dc.rights | Reserva de todos los derechos | es_ES |
dc.subject | FPGA | es_ES |
dc.subject | Essential bits | es_ES |
dc.subject | Fault injection | es_ES |
dc.subject.classification | ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES | es_ES |
dc.title | Reversing FPGA Architectures for Speeding up Fault Injection: does it pay? | es_ES |
dc.type | Comunicación en congreso | es_ES |
dc.type | Capítulo de libro | es_ES |
dc.identifier.doi | 10.1109/EDCC57035.2022.00023 | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2020-120271RB-I00/ES/ACELERADORES BASADOS EN FPGAS PARA REDES NEURONALES PROFUNDAS SUFICIENTEMENTE CONFIABLES PARA SISTEMAS DE AUTOMOCION/ | es_ES |
dc.rights.accessRights | Abierto | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Escola Tècnica Superior d'Enginyeria Informàtica | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors | es_ES |
dc.description.bibliographicCitation | Tuzov, I.; De-Andrés-Martínez, D.; Ruiz, JC. (2022). Reversing FPGA Architectures for Speeding up Fault Injection: does it pay?. IEEE. 81-88. https://doi.org/10.1109/EDCC57035.2022.00023 | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.conferencename | 18th European Dependable Computing Conference (EDCC 2022) | es_ES |
dc.relation.conferencedate | Septiembre 12-15,2022 | es_ES |
dc.relation.conferenceplace | Zaragoza, Spain | es_ES |
dc.relation.publisherversion | https://doi.org/10.1109/EDCC57035.2022.00023 | es_ES |
dc.description.upvformatpinicio | 81 | es_ES |
dc.description.upvformatpfin | 88 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.relation.pasarela | S\476132 | es_ES |