Mostrar el registro sencillo del ítem
dc.contributor.author | Tuzov, Ilya | es_ES |
dc.contributor.author | de-Andrés-Martínez, David | es_ES |
dc.contributor.author | Ruiz, Juan Carlos | es_ES |
dc.contributor.author | Hernández Luz, Carles | es_ES |
dc.date.accessioned | 2024-01-24T07:12:05Z | |
dc.date.available | 2024-01-24T07:12:05Z | |
dc.date.issued | 2023-04-19 | es_ES |
dc.identifier.isbn | 978-3-9819263-7-8 | es_ES |
dc.identifier.issn | 1938-1891 | es_ES |
dc.identifier.uri | http://hdl.handle.net/10251/202094 | |
dc.description.abstract | [EN] FPGA-based fault injection (FFI) is an indispensable technique for verification and dependability assessment of FPGA designs and prototypes. Existing FFI tools make use of Xilinx essential bits technology to locate the relevant fault targets in FPGA configuration memory (CM). Most FFI tools treat essential bits as black-box, while few of them are able to filter essential bits on the area basis in order to selectively target design components contained within the predefined Pblocks. This approach, however, remains insufficiently precise since the granularity of Pblocks in practice does not reach the smallest design components. This paper proposes an open-source FFI tool that enables much more fine-grained FFI experiments for Xilinx 7-series and Ultrascale+ FPGAs. By mapping the essential bits with the hierarchical netlist, it allows to precisely target any component in the design tree, up to an individual LUT or register, without the need for defining Pblocks (floorplanning). With minimal experimental effort it estimates the contribution of each DUT component into the resulting dependability features, and discovers weak points of the DUT. Through case studies we show how the proposed tool can be applied to different kinds of DUTs: from small-footprint microcontrollers, up to multicore RISC-V SoC. The correctness of FFI results is validated by means of RT-level and gate-level simulation-based fault injection. | es_ES |
dc.description.sponsorship | This work has received funding from (i) ECSEL Joint Undertaking (JU) under grant agreement No 877056, (ii) Agencia Estatal de Investigacion from Spain under grant agreement no. PCI2020-112092, (iii) European Unions Horizon 2020 research and innovation programme under grant agreement no. 871467, and (iv) Grant PID2020-120271RB-I00 funded by MCIN/AEI/ 10.13039/501100011033. Carles Hernandez is partially supported by Spanish Ministry of Science, Innovation and Universities under Ramon y Cajal, fellowship No. RYC2020-030685-I. | es_ES |
dc.language | Inglés | es_ES |
dc.publisher | IEEE | es_ES |
dc.relation.ispartof | 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) | es_ES |
dc.rights | Reserva de todos los derechos | es_ES |
dc.subject | Fault injection | es_ES |
dc.subject | FPGA | es_ES |
dc.subject | Configuration memory | es_ES |
dc.subject | Robustness assessment | es_ES |
dc.subject | RISC-V | es_ES |
dc.subject.classification | ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES | es_ES |
dc.title | BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypes | es_ES |
dc.type | Comunicación en congreso | es_ES |
dc.type | Artículo | es_ES |
dc.type | Capítulo de libro | es_ES |
dc.identifier.doi | 10.23919/DATE56975.2023.10137300 | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PCI2020-112092/ES/FRACTAL: A COGNITIVE FRACTAL AND SECURE EDGE-BASED ON A UNIQUE OPEN-SAFE-RELIABLE-LOW POWER HARDWARE PLATFORM NODE/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2020-120271RB-I00/ES/ACELERADORES BASADOS EN FPGAS PARA REDES NEURONALES PROFUNDAS SUFICIENTEMENTE CONFIABLES PARA SISTEMAS DE AUTOMOCION/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/EC/H2020/871467/EU | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/EC/H2020/877056/EU | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement///RYC2020-030685-I//AYUDA RYC/ | es_ES |
dc.rights.accessRights | Abierto | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Escola Tècnica Superior d'Enginyeria Informàtica | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors | es_ES |
dc.description.bibliographicCitation | Tuzov, I.; De-Andrés-Martínez, D.; Ruiz, JC.; Hernández Luz, C. (2023). BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypes. IEEE. https://doi.org/10.23919/DATE56975.2023.10137300 | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.conferencename | Design, Automation and Test in Europe Conference (DATE 2023) | es_ES |
dc.relation.conferencedate | Abril 17-19,2023 | es_ES |
dc.relation.conferenceplace | Antwerp, Belgium | es_ES |
dc.relation.publisherversion | https://doi.org/10.23919/DATE56975.2023.10137300 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.relation.pasarela | S\499456 | es_ES |