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dc.contributor.author | van Staveren, Job![]() |
es_ES |
dc.contributor.author | Padalia, Pinakin M.![]() |
es_ES |
dc.contributor.author | Charbon, Edoardo![]() |
es_ES |
dc.contributor.author | Almudéver, Carmen G.![]() |
es_ES |
dc.contributor.author | Scappucci, Giordano![]() |
es_ES |
dc.contributor.author | Babaie, Masoud![]() |
es_ES |
dc.contributor.author | Sebastiano, Fabio![]() |
es_ES |
dc.date.accessioned | 2024-09-23T18:02:44Z | |
dc.date.available | 2024-09-23T18:02:44Z | |
dc.date.issued | 2024-09 | es_ES |
dc.identifier.issn | 0018-9200 | es_ES |
dc.identifier.uri | http://hdl.handle.net/10251/208522 | |
dc.description.abstract | [EN] This article presents a family of sub-1-V, fully-CMOS voltage references adopting MOS devices in weak inversion to achieve continuous operation from room temperature (RT) down to cryogenic temperatures. Their accuracy limitations due to curvature, body effect, and mismatch are investigated and experimentally validated. Implemented in 40-nm CMOS, the references show a line regulation better than 2.7%/V from a supply as low as 0.99 V. By applying dynamic element matching (DEM) techniques, a spread of 1.2% (3 sigma ) from 4.2 to 300 K can be achieved, resulting in a temperature coefficient (TC) of 111 ppm/K. As the first significant statistical characterization extending down to cryogenic temperatures, the results demonstrate the ability of the proposed architectures to work under cryogenic harsh environments, such as space-and quantum-computing applications. | es_ES |
dc.description.sponsorship | This work was supported in part by Intel and in part by the Research Program OTP through The Netherlands Organization for Scientific Research (NWO) under Project 16278. | es_ES |
dc.language | Inglés | es_ES |
dc.publisher | Institute of Electrical and Electronics Engineers | es_ES |
dc.relation.ispartof | IEEE Journal of Solid-State Circuits | es_ES |
dc.rights | Reconocimiento (by) | es_ES |
dc.subject | Cryogenics | es_ES |
dc.subject | Temperature distribution | es_ES |
dc.subject | Resistors | es_ES |
dc.subject | Quantum computing | es_ES |
dc.subject | Logic gates | es_ES |
dc.subject | Threshold voltage | es_ES |
dc.subject | MOSFET | es_ES |
dc.subject | Body effect | es_ES |
dc.subject | Cryogenic CMOS (cryo-CMOS) | es_ES |
dc.subject | DTMOS | es_ES |
dc.subject | Extreme environment | es_ES |
dc.subject | MOS-based | es_ES |
dc.subject | Voltage references | es_ES |
dc.title | Cryo-CMOS Voltage References for the Ultrawide Temperature Range From 300 K Down to 4.2 K | es_ES |
dc.type | Artículo | es_ES |
dc.identifier.doi | 10.1109/JSSC.2024.3378768 | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/NWO//16278/ | es_ES |
dc.rights.accessRights | Abierto | es_ES |
dc.description.bibliographicCitation | Van Staveren, J.; Padalia, PM.; Charbon, E.; Almudéver, CG.; Scappucci, G.; Babaie, M.; Sebastiano, F. (2024). Cryo-CMOS Voltage References for the Ultrawide Temperature Range From 300 K Down to 4.2 K. IEEE Journal of Solid-State Circuits. 59(9):2884-2894. https://doi.org/10.1109/JSSC.2024.3378768 | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.publisherversion | https://doi.org/10.1109/JSSC.2024.3378768 | es_ES |
dc.description.upvformatpinicio | 2884 | es_ES |
dc.description.upvformatpfin | 2894 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.description.volume | 59 | es_ES |
dc.description.issue | 9 | es_ES |
dc.relation.pasarela | S\526448 | es_ES |
dc.contributor.funder | Netherlands Organization for Scientific Research | es_ES |