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dc.contributor.author | Andreu-Cerezo, Pablo | es_ES |
dc.contributor.author | López Rodríguez, Pedro Juan | es_ES |
dc.contributor.author | Hernández Luz, Carles | es_ES |
dc.date.accessioned | 2024-11-15T19:16:20Z | |
dc.date.available | 2024-11-15T19:16:20Z | |
dc.date.issued | 2024-12 | es_ES |
dc.identifier.issn | 1556-6056 | es_ES |
dc.identifier.uri | http://hdl.handle.net/10251/211882 | |
dc.description.abstract | [EN] Increasing the performance of safety-critical systems via introducing multicore processors is becoming the norm. However, when multiple cores access a shared cache, inter-core evictions become a relevant source of interference that must be appropriately controlled. To solve this issue, one can statically partition caches and remove the interference. Unfortunately, this comes at the expense of less flexibility and, in some cases, worse performance. In this context, enabling more flexible cache allocation policies requires additional monitoring support. This paper proposes HashTAG, a novel approach to accurately upper-bound inter-core eviction interference. HashTAG enables a low-overhead implementation of an Auxiliary Tag Directory to determine inter-core evictions. Our results show that no inter-task interference underprediction is possible with HashTAG while providing a 44% reduction in ATD area with only 1.14% median overprediction. | es_ES |
dc.description.sponsorship | This work was supported by CRUE-Universitat Politecnica de Valencia for open access charge. The work of Pablo Andreu was supported in part by "GVA" via "Subvenciones para la contratacion de personal investigador predoctoral" under Grant CIACIF/2021/412. The work of Carles Hernandez was partially supported in part by Spanish Ministry of Science, Innovation and Universities under "Ramon y Cajal" under Grant RYC2020-030685-I. | es_ES |
dc.language | Inglés | es_ES |
dc.publisher | Institute of Electrical and Electronics Engineers | es_ES |
dc.relation.ispartof | IEEE Computer Architecture Letters | es_ES |
dc.rights | Reconocimiento (by) | es_ES |
dc.subject | Multicore processing | es_ES |
dc.subject | Monitoring | es_ES |
dc.subject | Hardware | es_ES |
dc.subject | Timing | es_ES |
dc.subject | Task analysis | es_ES |
dc.subject | Certification | es_ES |
dc.subject | Safety | es_ES |
dc.subject | Contention | es_ES |
dc.subject | Caches | es_ES |
dc.subject | ATD | es_ES |
dc.subject | Multicore | es_ES |
dc.subject.classification | ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES | es_ES |
dc.title | Hashing ATD Tags for Low-Overhead Safe Contention Monitoring | es_ES |
dc.type | Artículo | es_ES |
dc.identifier.doi | 10.1109/LCA.2024.3401570 | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/GVA//CIACIF%2F2021%2F412/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/AEI//RYC2020-030685-I/ | es_ES |
dc.rights.accessRights | Abierto | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Instituto de Instrumentación para Imagen Molecular - Institut d'Instrumentació per a Imatge Molecular | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Escola Tècnica Superior d'Enginyeria Informàtica | es_ES |
dc.description.bibliographicCitation | Andreu-Cerezo, P.; López Rodríguez, PJ.; Hernández Luz, C. (2024). Hashing ATD Tags for Low-Overhead Safe Contention Monitoring. IEEE Computer Architecture Letters. 23(2):166-169. https://doi.org/10.1109/LCA.2024.3401570 | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.publisherversion | https://doi.org/10.1109/LCA.2024.3401570 | es_ES |
dc.description.upvformatpinicio | 166 | es_ES |
dc.description.upvformatpfin | 169 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.description.volume | 23 | es_ES |
dc.description.issue | 2 | es_ES |
dc.relation.pasarela | S\531798 | es_ES |
dc.contributor.funder | Generalitat Valenciana | es_ES |
dc.contributor.funder | Agencia Estatal de Investigación | es_ES |
dc.contributor.funder | Universitat Politècnica de València | es_ES |