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A Dynamic Power-Aware Partitioner with Real-Time Task Migration for Embedded Multicore Processors

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A Dynamic Power-Aware Partitioner with Real-Time Task Migration for Embedded Multicore Processors

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dc.contributor.advisor Sahuquillo Borrás, Julio es_ES
dc.contributor.advisor Petit Martí, Salvador Vicente es_ES
dc.contributor.author March Cabrelles, José Luis es_ES
dc.date.accessioned 2013-06-18T12:01:29Z
dc.date.available 2013-06-18T12:01:29Z
dc.date.created 2012-10-26
dc.date.issued 2013-06-18
dc.identifier.uri http://hdl.handle.net/10251/29847
dc.description.abstract [ES] Analizar el impacto de permitir que las tareas de tiempo real puedan migrar su ejecución de un core a otro, sobre el consumo en sistemas empotrados multicore. es_ES
dc.description.abstract [EN] A major design issue in embedded systems is reducing the power consumption since batteries have a limited energy budget. For this purpose, several techniques such as Dynamic Voltage and Frequency Scaling (DVFS) or task migration are being used. DVFS circuitry allows reducing power by selecting the optimal voltage supply, while task migration achieves this effect by balancing the workload among cores. This work focuses on power-aware scheduling allowing task migration to reduce energy consumption in multicore embedded systems implementing DVFS capabilities. To address energy savings, the devised schedulers follow two main rules: migrations are allowed at specific points of time and only one task is allowed to migrate each time. Two algorithms have been proposed working under real-time constraints. The simpler algorithm, namely, Single Option Migration (SOM) only checks one target core before performing a migration. In contrast, the Multiple Option Migration (MOM) searches the optimal target core. In general, the MOM algorithm achieves better energy savings than the SOM algorithm, although differences are wider for a reduced number of cores and frequency/voltage levels. Moreover, the MOM algorithm reduces energy consumption as much as 40% over the typical Worst Fit (WF) strategy. es_ES
dc.format.extent 48 es_ES
dc.language Inglés es_ES
dc.publisher Universitat Politècnica de València es_ES
dc.rights Reconocimiento - No comercial - Sin obra derivada (by-nc-nd) es_ES
dc.subject Migración de Tareas de Tiempo Real es_ES
dc.subject Reducción de Consumo es_ES
dc.subject Distribución Dinámica es_ES
dc.subject Sistemas Empotrados Multinúcleo es_ES
dc.subject Real-Time Task Migration es_ES
dc.subject Power-Aware es_ES
dc.subject Dynamic Partitioning es_ES
dc.subject Multicore Embedded Systems es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.subject.other Máster Universitario en Ingeniería de Computadores-Màster Universitari en Enginyeria de Computadors es_ES
dc.title A Dynamic Power-Aware Partitioner with Real-Time Task Migration for Embedded Multicore Processors es_ES
dc.type Tesis de máster es_ES
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Servicio de Alumnado - Servei d'Alumnat es_ES
dc.description.bibliographicCitation March Cabrelles, JL. (2012). A Dynamic Power-Aware Partitioner with Real-Time Task Migration for Embedded Multicore Processors. http://hdl.handle.net/10251/29847 es_ES
dc.description.accrualMethod Archivo delegado es_ES


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