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Combining Recency of Information with Selective Random and a Victim Cache in Last-Level Caches

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Combining Recency of Information with Selective Random and a Victim Cache in Last-Level Caches

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Valero Bresó, A.; Sahuquillo Borrás, J.; Petit Martí, SV.; López Rodríguez, PJ.; Duato Marín, JF. (2012). Combining Recency of Information with Selective Random and a Victim Cache in Last-Level Caches. ACM Transactions on Architecture and Code Optimization. 9(3):1-20. doi:10.1145/2355585.2355589

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/30306

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Title: Combining Recency of Information with Selective Random and a Victim Cache in Last-Level Caches
Author: Valero Bresó, Alejandro Sahuquillo Borrás, Julio Petit Martí, Salvador Vicente López Rodríguez, Pedro Juan Duato Marín, José Francisco
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Issued date:
Abstract:
Memory latency has become an important performance bottleneck in current microprocessors. This problem aggravates as the number of cores sharing the same memory controller increases. To palliate this problem, a common ...[+]
Subjects: Last-Level Cache , MRU-Tour , Replacement algorithm
Copyrigths: Cerrado
Source:
ACM Transactions on Architecture and Code Optimization. (issn: 1544-3566 )
DOI: 10.1145/2355585.2355589
Publisher:
Association for Computing Machinery (ACM)
Publisher version: http://dx.doi.org/10.1145/2355585.2355589
Thanks:
This work was supported by the Spanish MICINN, Consolider Programme, and Plan E funds, as well as European Commission FEDER funds, under Grants CSD2006-00046 and TIN2009-14475-C04-01.
Type: Artículo

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