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Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors

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Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors

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Lodde, M. (2014). Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors [Tesis doctoral no publicada]. Universitat Politècnica de València. doi:10.4995/Thesis/10251/35325.

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/35325

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Title: Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors
Author:
Director(s): Flich Cardo, José
UPV Unit: Universitat Politècnica de València. Departamento de Sistemas Informáticos y Computación - Departament de Sistemes Informàtics i Computació
Read date / Event date:
2014-01-14
Issued date:
Abstract:
La jerarquía de caches y la red en el chip (NoC) son dos componentes clave de los chip multiprocesadores (CMPs). La mayoría del trafico en la NoC se debe a mensajes que las caches envían según lo que establece el protocolo ...[+]
Subjects: Chip multiprocessors , Computer architecture , Cache hierarchy , Cache coherence protocols , Network-on-chip
Copyrigths: Reserva de todos los derechos
DOI: 10.4995/Thesis/10251/35325
Type: Tesis doctoral

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