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Low-complexity low-density parity check decoding algorithm for high-speed very large scale integration implementation

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Low-complexity low-density parity check decoding algorithm for high-speed very large scale integration implementation

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Angarita Preciado, FE.; Marín-Roig Ramón, J.; Almenar Terre, V.; Valls Coquillat, J. (2012). Low-complexity low-density parity check decoding algorithm for high-speed very large scale integration implementation. IET Communications. 6(16):2575-2581. doi:10.1049/iet-com.2011.0542

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/35734

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Title: Low-complexity low-density parity check decoding algorithm for high-speed very large scale integration implementation
Author:
UPV Unit: Universitat Politècnica de València. Instituto Universitario de Telecomunicación y Aplicaciones Multimedia - Institut Universitari de Telecomunicacions i Aplicacions Multimèdia
Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica
Universitat Politècnica de València. Departamento de Comunicaciones - Departament de Comunicacions
Issued date:
Abstract:
This study proposes a new low-complexity decoding algorithm for low-density parity check codes, which is a variation of the offset min-sum algorithm and achieves a similar performance with lower hardware cost. A finite ...[+]
Subjects: LDPC CODES , VLSI , Decoding , Message passing , Parity check codes
Copyrigths: Cerrado
Source:
IET Communications. (issn: 1751-8628 )
DOI: 10.1049/iet-com.2011.0542
Publisher:
Institution of Engineering and Technology (IET)
Publisher version: http://dx.doi.org/10.1049/iet-com.2011.0542
Thanks:
This research was supported by Fondo Europeo de Desarrollo Regional (FEDER), the Spanish Ministerio de Ciencia e Innovacion, under grant numbers TEC2008-06787 and TEC2011-27916.
Type: Artículo

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