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A dynamic power-aware partitioner with task migration for multicore embedded systems

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A dynamic power-aware partitioner with task migration for multicore embedded systems

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March Cabrelles, JL.; Sahuquillo Borrás, J.; Petit Martí, SV.; Hassan Mohamed, H.; Duato Marín, JF. (2011). A dynamic power-aware partitioner with task migration for multicore embedded systems. En Euro-Par 2011 Parallel Processing. Springer Verlag (Germany). 2011(6852):218-229. doi:10.1007/978-3-642-23400-2_21

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/35796

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Title: A dynamic power-aware partitioner with task migration for multicore embedded systems
Author:
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Issued date:
Abstract:
Nowadays, a key design issue in embedded systems is how to reduce the power consumption, since batteries have a limited energy budget. For this purpose, several techniques such as Dynamic Voltage Scaling (DVS) or task ...[+]
Subjects: Design issues , Dynamic voltage scaling , Energy budgets , Multicore embedded system , Optimal target , Power-aware , Reducing power , Task migration , Voltage supply
Copyrigths: Reserva de todos los derechos
ISBN: 978-3-642-23399-9
Source:
Euro-Par 2011 Parallel Processing. (issn: 0302-9743 )
DOI: 10.1007/978-3-642-23400-2_21
Publisher:
Springer Verlag (Germany)
Publisher version: http://link.springer.com/chapter/10.1007/978-3-642-23400-2_21
Conference name: 17th International Conference, Euro-Par 2011
Conference place: Bordeaux, France
Conference date: August 29 - September 2, 2011
Series: Lecture Notes in Computer Science;vol. 6852
Project ID: info:eu-repo/grantAgreement/EC/FP7/217068/EU
Type: Capítulo de libro

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