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dc.contributor.author | Angarita Preciado, Fabián Enrique![]() |
es_ES |
dc.contributor.author | Sansaloni Balaguer, Trinidad Mª![]() |
es_ES |
dc.contributor.author | Canet Subiela, Mª José![]() |
es_ES |
dc.contributor.author | Valls Coquillat, Javier![]() |
es_ES |
dc.date.accessioned | 2014-04-03T18:41:42Z | |
dc.date.issued | 2012-02 | |
dc.identifier.issn | 1939-8018 | |
dc.identifier.uri | http://hdl.handle.net/10251/36821 | |
dc.description.abstract | This paper presents an architecture for high-throughput decoding of high-rate Low-Density Parity-Check (LDPC) codes. The proposed architecture is a modification of the sliced message passing (SMP) decoding architecture which overlaps the check-node and variable-node update stages, achieving a good tradeoff between area and throughput, and also, high hardware utilization efficiency (HUE). The proposed modification does not affect the performance of the SMP algorithm and yields an area reduction of 33%. As an example, SMP architecture and the proposed modification was synthesized in a 90 nm CMOS process for the 2048-bit LDPC code of the IEEE802.3an standard with 16 iterations achieving a throughput of 5.9 Gbps with 15.3 mm2 and 6.2 Gbps with 10.2 mm2, respectively. | es_ES |
dc.description.sponsorship | This research was supported by FEDER and Spanish Ministerio de Ciencia e Innovacion under Grant No. TEC2008-06787. | en_EN |
dc.format.extent | 6 | es_ES |
dc.language | Inglés | es_ES |
dc.publisher | Springer Verlag (Germany) | es_ES |
dc.relation.ispartof | Journal of Signal Processing Systems | es_ES |
dc.rights | Reserva de todos los derechos | es_ES |
dc.subject | LDPC decoder | es_ES |
dc.subject | High speed | es_ES |
dc.subject | VLSI | es_ES |
dc.subject | Sliced message passing architecture | es_ES |
dc.subject.classification | TECNOLOGIA ELECTRONICA | es_ES |
dc.title | Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes | es_ES |
dc.type | Artículo | es_ES |
dc.embargo.lift | 10000-01-01 | |
dc.embargo.terms | forever | es_ES |
dc.identifier.doi | 10.1007/s11265-011-0580-3 | |
dc.relation.projectID | info:eu-repo/grantAgreement/MICINN//TEC2008-06787/ES/ARQUITECTURAS DE FEC PARA SISTEMAS DE COMUNICACIONES DE MUY ALTA VELOCIDAD/ | es_ES |
dc.rights.accessRights | Cerrado | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Instituto Universitario de Telecomunicación y Aplicaciones Multimedia - Institut Universitari de Telecomunicacions i Aplicacions Multimèdia | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica | es_ES |
dc.description.bibliographicCitation | Angarita Preciado, FE.; Sansaloni Balaguer, TM.; Canet Subiela, MJ.; Valls Coquillat, J. (2012). Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes. Journal of Signal Processing Systems. 66(2):99-104. https://doi.org/10.1007/s11265-011-0580-3 | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.publisherversion | http://dx.doi.org/10.1007/s11265-011-0580-3 | es_ES |
dc.description.upvformatpinicio | 99 | es_ES |
dc.description.upvformatpfin | 104 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.description.volume | 66 | es_ES |
dc.description.issue | 2 | es_ES |
dc.relation.senia | 212851 | |
dc.contributor.funder | Ministerio de Ciencia e Innovación | es_ES |
dc.contributor.funder | European Regional Development Fund | es_ES |
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