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Cost-efficient on-chip routing implementations for CMP and MPSoC systems

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Cost-efficient on-chip routing implementations for CMP and MPSoC systems

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Rodrigo Mocholí, S.; Flich Cardo, J.; Roca Pérez, A.; Medardoni, S.; Bertozzi, D.; Camacho Villanueva, J.; Silla Jiménez, F.... (2011). Cost-efficient on-chip routing implementations for CMP and MPSoC systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30(4):534-547. doi:10.1109/TCAD.2011.2119150

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/37053

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Title: Cost-efficient on-chip routing implementations for CMP and MPSoC systems
Author:
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Universitat Politècnica de València. Grupo de Arquitecturas Paralelas
Issued date:
Abstract:
[EN] The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while ...[+]
Subjects: Fault-tolerance , Logic design , Networks-on-chip , Routing
Copyrigths: Cerrado
Source:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. (issn: 0278-0070 )
DOI: 10.1109/TCAD.2011.2119150
Publisher:
Institute of Electrical and Electronics Engineers (IEEE)
Publisher version: http://doi.org/10.1109/TCAD.2011.2119150
Project ID: info:eu-repo/grantAgreement/EC/FP7/248972
Thanks:
This work was supported by the Spanish MEC and MICINN, as well as by the European Commission FEDER funds, under Grants CSD2006-00046 and TIN2009- 14475-C04. This work was supported in part by the Project NaNoC (Project ...[+]
Type: Artículo

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