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Hardware-based generation of independent subtraces of instructions in clustered processors

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Hardware-based generation of independent subtraces of instructions in clustered processors

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Ubal Tena, R.; Sahuquillo Borrás, J.; Petit Martí, SV.; López Rodríguez, PJ.; Duato Marín, JF. (2013). Hardware-based generation of independent subtraces of instructions in clustered processors. IEEE Transactions on Computers. 62(5):944-955. https://doi.org/10.1109/TC.2012.42

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/38251

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Title: Hardware-based generation of independent subtraces of instructions in clustered processors
Author: Ubal Tena, Rafael Sahuquillo Borrás, Julio Petit Martí, Salvador Vicente López Rodríguez, Pedro Juan Duato Marín, José Francisco
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Issued date:
Abstract:
Multicore chips are currently dominating the microprocessor market as designs that improve performance and sustain power consumption. However, complex core features must be still considered to provide good performance for ...[+]
Subjects: Clustered Processors , Trace Caches , Hardware extraction of paralelism
Copyrigths: Reserva de todos los derechos
Source:
IEEE Transactions on Computers. (issn: 0018-9340 )
DOI: 10.1109/TC.2012.42
Publisher:
Institute of Electrical and Electronics Engineers (IEEE)
Publisher version: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6148217
Project ID:
info:eu-repo/grantAgreement/EC/FP7/287759/EU/High Performance and Embedded Architecture and Compilation/
Spanish MICINN
...[+]
info:eu-repo/grantAgreement/EC/FP7/287759/EU/High Performance and Embedded Architecture and Compilation/
Spanish MICINN
Consolider Programme
Plan E funds
info:eu-repo/grantAgreement/MICINN//TIN2009-14475-C04-01/ES/Arquitecturas De Servidores, Aplicaciones Y Servicios/
info:eu-repo/grantAgreement/MEC//CSD2006-00046/ES/High-performance, reliable architectures for data centers and Internet servers/
[-]
Description: © 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Thanks:
This work was supported by the Spanish MICINN, Consolider Programme, and Plan E funds, as well as European Commission FEDER funds, under Grants CSD2006-00046 and TIN2009-14475-C04-01.
Type: Artículo

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