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Hardware-based generation of independent subtraces of instructions in clustered processors

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Hardware-based generation of independent subtraces of instructions in clustered processors

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Ubal Tena, R.; Sahuquillo Borrás, J.; Petit Martí, SV.; López Rodríguez, PJ.; Duato Marín, JF. (2013). Hardware-based generation of independent subtraces of instructions in clustered processors. IEEE Transactions on Computers. 62(5):944-955. doi:10.1109/TC.2012.42.

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Título: Hardware-based generation of independent subtraces of instructions in clustered processors
Autor:
Entidad UPV: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Fecha difusión:
Resumen:
Multicore chips are currently dominating the microprocessor market as designs that improve performance and sustain power consumption. However, complex core features must be still considered to provide good performance for ...[+]
Palabras clave: Clustered Processors , Trace Caches , Hardware extraction of paralelism
Derechos de uso: Reserva de todos los derechos
Fuente:
IEEE Transactions on Computers. (issn: 0018-9340 )
DOI: 10.1109/TC.2012.42
Editorial:
Institute of Electrical and Electronics Engineers (IEEE)
Versión del editor: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6148217
Descripción: © 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Patrocinador:
Spanish MICINN
Consolider Programme
Plan E funds
European Commission FEDER funds [CSD2006-00046 and TIN2009-14475-C04-01]
Tipo: Artículo

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