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Efficient built-in NoC support for gather operations in invalidation-based coherence protocols

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Efficient built-in NoC support for gather operations in invalidation-based coherence protocols

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Lodde, M. (2013). Efficient built-in NoC support for gather operations in invalidation-based coherence protocols. http://hdl.handle.net/10251/44966.

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Title: Efficient built-in NoC support for gather operations in invalidation-based coherence protocols
Author:
Director(s): Flich Cardo, José
UPV Unit: Universitat Politècnica de València. Servicio de Alumnado - Servei d'Alumnat
Read date / Event date:
2013-02-08
Issued date:
Abstract:
[EN] A dedicated control network is used to transmit acknowledgement messages generated by the coherence protocol, thus reducing the traffic in the regular NoC and improving the overall system performance


[ES] Se propone una red dedicada para transmitir los mensajes de acknowledgement generados por el protocolo de coherencia, con el objetivo de reducir el tráfico en la NoC, mejorando así las prestaciones del sistema
Subjects: Chip multiprocesador , Jerarquia de caches , Red en el chip , Chip multiprocessor , Cache hierarchy , Network-on-chip
Copyrigths: Reconocimiento - No comercial - Sin obra derivada (by-nc-nd)
degree: Máster Universitario en Ingeniería de Computadores-Màster Universitari en Enginyeria de Computadors
Type: Tesis de máster

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