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Explicit communication and synchronization in SARC

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Explicit communication and synchronization in SARC

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Nombre: M. Katevenis;V. ...
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dc.contributor.author Katevenis, Manolis G.H. es_ES
dc.contributor.author Papaefstathiou, Vassilis es_ES
dc.contributor.author Kavadias, Stamatis es_ES
dc.contributor.author Pnevmatikatos, Dionisios es_ES
dc.contributor.author Nikolopoulos, Dimitros S. es_ES
dc.contributor.author Silla Jiménez, Federico es_ES
dc.date.accessioned 2014-12-05T11:36:56Z
dc.date.available 2014-12-05T11:36:56Z
dc.date.issued 2010-10
dc.identifier.issn 0272-1732
dc.identifier.uri http://hdl.handle.net/10251/45222
dc.description.abstract [EN] A new network interface optimized for SARC supports synchronization and explicit communication and provides a robust mechanism for event responses. Full-system simulation of the authors' design achieved a 10- to 40-percent speed increase over traditional cache architectures on 64 cores, a two- to four-fold decrease in on-chip network traffic, and a three- to five-fold decrease in lock and barrier latency. es_ES
dc.description.sponsorship This work is supported by the European Commission in the context of the projects SARC (FP6 IP #27648), Unisix (Marie-Curie #509595), and the HiPEAC Network of Excellence (NoE 004408). We also thank, for their assistance in designing the architecture and their collaboration in the SARC project, Alex Ramirez, Georgi Gaydadjiev, Angelos Bilas, George Kalokerinos, George Nikiforos, Dimitris Tsaliagos, Xiaojun Yang, Spyros Lyberis, Christos Sotiriou, and Michael Ligerakis.
dc.language Inglés es_ES
dc.publisher Institute of Electrical and Electronics Engineers (IEEE) es_ES
dc.relation.ispartof IEEE Micro es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject SARC es_ES
dc.subject Configurable local memory es_ES
dc.subject Explicit communication es_ES
dc.subject Interprocessor communication es_ES
dc.subject Scratchpad es_ES
dc.subject Synchronization es_ES
dc.subject User-level RDMA es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.title Explicit communication and synchronization in SARC es_ES
dc.type Artículo es_ES
dc.identifier.doi 10.1109/MM.2010.77
dc.relation.projectID info:eu-repo/grantAgreement/EC/FP6/509595/EU/Unifying High-speed Interconnects/UNISIX/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/EC/FP6/027648/EU/Scalable Computer Architecture/SARC/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/EC/FP6-IST/004408/EU/High-performance embedded architectures and compilers/HIPEAC/ es_ES
dc.rights.accessRights Cerrado es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.description.bibliographicCitation Katevenis, MG.; Papaefstathiou, V.; Kavadias, S.; Pnevmatikatos, D.; Nikolopoulos, DS.; Silla Jiménez, F. (2010). Explicit communication and synchronization in SARC. IEEE Micro. 30(5):30-41. doi:10.1109/MM.2010.77 es_ES
dc.description.accrualMethod S es_ES
dc.relation.publisherversion http://dx.doi.org/10.1109/MM.2010.77 es_ES
dc.description.upvformatpinicio 30 es_ES
dc.description.upvformatpfin 41 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 30 es_ES
dc.description.issue 5 es_ES
dc.relation.senia 216225
dc.contributor.funder European Commission


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