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Cache-Hierarchy contention-aware scheduling in CMPs

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Cache-Hierarchy contention-aware scheduling in CMPs

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Feliu Pérez, J.; Petit Martí, SV.; Sahuquillo Borrás, J.; Duato Marín, JF. (2014). Cache-Hierarchy contention-aware scheduling in CMPs. IEEE Transactions on Parallel and Distributed Systems. 25(3):581-590. doi:10.1109/TPDS.2013.61

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/49705

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Title: Cache-Hierarchy contention-aware scheduling in CMPs
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
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To improve chip multiprocessor (CMP) performance, recent research has focused on scheduling strategies to mitigate main memory bandwidth contention. Nowadays, commercial CMPs implement multilevel cache hierarchies that are ...[+]
Subjects: Contention-aware scheduling , Contention points , Shared caches , Cache hierarchy , Memory contention
Copyrigths: Reserva de todos los derechos
IEEE Transactions on Parallel and Distributed Systems. (issn: 1045-9219 )
DOI: 10.1109/TPDS.2013.61
Institute of Electrical and Electronics Engineers (IEEE)
Publisher version: http://doi.ieeecomputersociety.org/10.1109/TPDS.2013.61
Description: © © 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works
This work was supported by the Spanish MINECO under Grant TIN2012-38341-C04-01, and by the Universitat Politecnica de Valencia under Grant PAID-05-12 SP20120748.
Type: Artículo

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