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Efficient register renaming and recovery for high-performance processors

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Efficient register renaming and recovery for high-performance processors

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Petit Martí, SV.; Ubal Tena, R.; Sahuquillo Borrás, J.; López Rodríguez, PJ. (2014). Efficient register renaming and recovery for high-performance processors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22(7):1506-1514. doi:10.1109/TVLSI.2013.2270001

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Título: Efficient register renaming and recovery for high-performance processors
Autor:
Entidad UPV: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Fecha difusión:
Resumen:
Modern superscalar processors implement register renaming using either random access memory (RAM) or content-addressable memories (CAM) tables. The design of these structures should address both access time and ...[+]
Palabras clave: Content-addressable memory (CAM) complexity , Energy consumption , Energy efficiency , Misspeculation recovery , Register renaming.
Derechos de uso: Reserva de todos los derechos
Fuente:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. (issn: 1063-8210 )
DOI: 10.1109/TVLSI.2013.2270001
Editorial:
Institute of Electrical and Electronics Engineers (IEEE)
Versión del editor: http://dx.doi.org/10.1109/TVLSI.2013.2270001
Descripción: © © 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.”
Agradecimientos:
This work was supported in part by the Spanish MINECO under Grant TIN2012-38341-C04-01.
Tipo: Artículo

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