- -

Runtime home mapping for effective memory resource usage

RiuNet: Institutional repository of the Polithecnic University of Valencia

Share/Send to

Cited by

Statistics

Runtime home mapping for effective memory resource usage

Show full item record

Lodde, M.; Flich Cardo, J. (2014). Runtime home mapping for effective memory resource usage. Microprocessors and Microsystems. 38(4):276-291. doi:10.1016/j.micpro.2014.03.008

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/50718

Files in this item

Item Metadata

Title: Runtime home mapping for effective memory resource usage
Author:
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Issued date:
Abstract:
In tiled Chip Multiprocessors (CMPs) last-level cache (LLC) banks are usually shared but distributed among the tiles. A static mapping of cache blocks to the LLC banks leads to poor efficiency since a block may be mapped ...[+]
Subjects: Chip multiprocessors , Network-on-chip , Cache hierarchy , Coherence protocols
Copyrigths: Reserva de todos los derechos
Source:
Microprocessors and Microsystems. (issn: 0141-9331 )
DOI: 10.1016/j.micpro.2014.03.008
Publisher:
Elsevier
Publisher version: http://dx.doi.org/10.1016/j.micpro.2014.03.008
Type: Artículo

This item appears in the following Collection(s)

Show full item record