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Design of Hybrid Second-Level Caches

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Design of Hybrid Second-Level Caches

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Valero Bresó, A.; Sahuquillo Borrás, J.; Petit Martí, SV.; López Rodríguez, PJ.; Duato Marín, JF. (2015). Design of Hybrid Second-Level Caches. IEEE Transactions on Computers. 64(7):1884-1897. doi:10.1109/TC.2014.2346185

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/63858

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Title: Design of Hybrid Second-Level Caches
Author: Valero Bresó, Alejandro Sahuquillo Borrás, Julio Petit Martí, Salvador Vicente López Rodríguez, Pedro Juan Duato Marín, José Francisco
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Issued date:
Abstract:
In recent years, embedded dynamic random-access memory (eDRAM) technology has been implemented in last-level caches due to its low leakage energy consumption and high density. However, the fact that eDRAM presents slower ...[+]
Subjects: Cache memories , eDRAM , Energy-aware systems , Hybrid systems , SRAM
Copyrigths: Reserva de todos los derechos
Source:
IEEE Transactions on Computers. (issn: 0018-9340 )
DOI: 10.1109/TC.2014.2346185
Publisher:
Institute of Electrical and Electronics Engineers (IEEE)
Publisher version: http://dx.doi.org/ 10.1109/TC.2014.2346185
Project ID:
Spanish Ministerio de Economia y Competitividad (MINECO)
FEDER/ TIN2012-38341-C04-01
Intel Early Career Honor Programme Award
Intel Doctoral Student Honor Programme Award
Description: “©2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.”
Thanks:
This work was supported by the Spanish Ministerio de Economia y Competitividad (MINECO) and FEDER funds under Grant TIN2012-38341-C04-01. Additionally, it was also supported by the Intel Early Career Honor Programme Award ...[+]
Type: Artículo

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