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Impact of partitioning cache schemes on the cache hierarchy of SMT processors

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Impact of partitioning cache schemes on the cache hierarchy of SMT processors

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Kenyon, S.; López, S.; Sahuquillo Borrás, J. (2015). Impact of partitioning cache schemes on the cache hierarchy of SMT processors. IEEE. doi:10.1109/HPCC-CSS-ICESS.2015.127

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/64646

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Title: Impact of partitioning cache schemes on the cache hierarchy of SMT processors
Author: Kenyon, Samantha López, Sonia Sahuquillo Borrás, Julio
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Issued date:
Abstract:
Power consumption is becoming an increasingly important component of processor design. As technology node shrinks both static and dynamic power become more relevant. This is particularly critical for the cache hierarchy. ...[+]
Subjects: Cache partitioning , Drowsy caches , Phase adaptive cache
Copyrigths: Reserva de todos los derechos
ISBN: 978-1-4799-8936-2
DOI: 10.1109/HPCC-CSS-ICESS.2015.127
Publisher:
IEEE
Publisher version: http://dx.doi.org/10.1109/HPCC-CSS-ICESS.2015.127
Conference name: 17th IEEE International Conference on High Performance Computing and Communications (HPCC 2015)
Conference place: New York, USA
Conference date: August 24-26, 2015
Description: © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Thanks:
This work was supported by the Spanish Ministerio de Economía y Competitividad (MINECO) and by FEDER funds under Grant TIN2012–38341–C04–01.
Type: Comunicación en congreso

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