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Speeding-up the fault-tolerance analysis of interconnection networks

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Speeding-up the fault-tolerance analysis of interconnection networks

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Bermudez Garzon, DF.; Gómez Requena, C.; López Rodríguez, PJ.; Gómez Requena, ME. (2015). Speeding-up the fault-tolerance analysis of interconnection networks. IEEE. doi:10.1109/HPCSim.2015.7237035

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/65733

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Title: Speeding-up the fault-tolerance analysis of interconnection networks
Author:
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Issued date:
Abstract:
Analyzing the fault-tolerance of interconnection networks implies checking the connectivity of each sourcedestination pair. The size of the exploration space of such operation skyrockets with the network size and with ...[+]
Subjects: Fat-Tree , MINs , Fault-tolerance , CUDA
Copyrigths: Reserva de todos los derechos
ISBN: 978-1-4673-7811-6
DOI: 10.1109/HPCSim.2015.7237035
Publisher:
IEEE
Publisher version: http://dx.doi.org/10.1109/HPCSim.2015.7237035
Conference name: International Conference on High Performance Computing & Simulation (HPCS 2015)
Conference place: Amsterdam, the Netherlands
Conference date: July 20-24, 2015
Description: © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works
Type: Comunicación en congreso

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