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Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes

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Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes

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Lorente Garcés, VJ.; Valero Bresó, A.; Sahuquillo Borrás, J.; Petit Martí, SV.; Canal, R.; López Rodríguez, PJ.; Duato Marín, JF. (2013). Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes. IEEE, ACM. https://doi.org/10.7873/DATE.2013.031

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/75168

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Title: Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes
Author: Lorente Garcés, Vicente Jesús Valero Bresó, Alejandro Sahuquillo Borrás, Julio Petit Martí, Salvador Vicente Canal, Ramón López Rodríguez, Pedro Juan Duato Marín, José Francisco
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Universitat Politècnica de València. Escola Tècnica Superior d'Enginyeria Informàtica
Issued date:
Abstract:
Low-power modes in modern microprocessors rely on low frequencies and low voltages to reduce the energy budget. Nevertheless, manufacturing induced parameter variations can make SRAM cells unreliable producing hard ...[+]
Copyrigths: Reserva de todos los derechos
ISBN: 978-3-9815370-0-0
Source:
(issn: 1530-1591 )
DOI: 10.7873/DATE.2013.031
Publisher:
IEEE, ACM
Publisher version: http://dx.doi.org/10.7873/DATE.2013.031
Conference name: Design, Automation and Test in Europe (DATE 2013)
Conference place: Grenoble, France
Conference date: March 18-22, 2013
Project ID:
info:eu-repo/grantAgreement/EC/FP7/248789/EU/TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS/
info:eu-repo/grantAgreement/MICINN//TIN2010-18368/ES/MICROARQUITECTURA Y COMPILADORES PARA FUTUROS PROCESADORES II/
...[+]
info:eu-repo/grantAgreement/EC/FP7/248789/EU/TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS/
info:eu-repo/grantAgreement/MICINN//TIN2010-18368/ES/MICROARQUITECTURA Y COMPILADORES PARA FUTUROS PROCESADORES II/
MICINN-FEDER/CSD2006-00046
info:eu-repo/grantAgreement/MICINN//TIN2009-14475-C04-01/ES/Arquitecturas De Servidores, Aplicaciones Y Servicios/
GC/2009SGR1250
MINECO/TIN2012-38341-C04-01
[-]
Description: ©2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Thanks:
This work was supported by the Spanish MICINN (TIN2010-18368) with the Consolider-Ingenio 2010 Programme co-funded by the European Commission FEDER funds (CSD2006-00046) and co-funded with the Plan E funds (TIN2009-14475-C04-01). ...[+]
Type: Comunicación en congreso

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