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Enhanced Grid Fundamental Positive-Sequence Digital Synchronization Structure

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Enhanced Grid Fundamental Positive-Sequence Digital Synchronization Structure

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dc.contributor.author Alfonso Gil, José Carlos es_ES
dc.contributor.author Vague Cardona, José Joaquín es_ES
dc.contributor.author Orts-Grau, Salvador es_ES
dc.contributor.author Gimeno Sales, Francisco José es_ES
dc.contributor.author Segui-Chilet, Salvador es_ES
dc.date.accessioned 2017-03-27T12:51:01Z
dc.date.available 2017-03-27T12:51:01Z
dc.date.issued 2013-01
dc.identifier.issn 0885-8977
dc.identifier.uri http://hdl.handle.net/10251/79113
dc.description.abstract The second-order generalized integrator (SOGI) filter and delayed signal cancellation (DSC) structures have been used separately in order to improve the synchronization systems response in adverse grid conditions. Taking into account its characteristics, this paper proposes a new structure based on a combination of SOGI filter, DSC method, and a software phase-locked loop (S). The enhanced synchronization structure is used to estimate the fundamental positive-sequence component of grid voltages (v(s1)(+)) in distorted and asymmetric three-phase systems. DSC and SOGI working in the stationary alpha-beta frame are used to obtain the v(s1)(+) component, while S in a synchronous reference frame (SRF) or the d-q frame is used to obtain v(s1)(+) pulsation and phase. The cutting frequency of the SOGI filter is selected by taking into account the capability of DSC to eliminate determinate order harmonic components. The bandwidth of S is adjusted to achieve a good relation between dynamic response and filtering capability. The SOGI filter has an adaptive structure to modify its cutting frequency when a variation in the fundamental frequency of grid voltages occurs. The performance of the proposed structure is verified through simulations and experimental cases, using a grid set of voltages that include all nonefficient voltage components (distortion, asymmetries, and negative-sequence components). es_ES
dc.language Inglés es_ES
dc.publisher Institute of Electrical and Electronics Engineers (IEEE) es_ES
dc.relation.ispartof IEEE Transactions on Power Delivery es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject Asymmetries es_ES
dc.subject Delayed signal cancellation es_ES
dc.subject Distortion es_ES
dc.subject Harmonics es_ES
dc.subject Phase-locked loop es_ES
dc.subject Second-order generalized integrator es_ES
dc.subject Synchronization systems es_ES
dc.subject.classification TECNOLOGIA ELECTRONICA es_ES
dc.title Enhanced Grid Fundamental Positive-Sequence Digital Synchronization Structure es_ES
dc.type Artículo es_ES
dc.identifier.doi 10.1109/TPWRD.2012.2219559
dc.rights.accessRights Cerrado es_ES
dc.contributor.affiliation Universitat Politècnica de València. Escuela Técnica Superior de Ingeniería del Diseño - Escola Tècnica Superior d'Enginyeria del Disseny es_ES
dc.contributor.affiliation Universitat Politècnica de València. Escuela Técnica Superior de Ingenieros de Telecomunicación - Escola Tècnica Superior d'Enginyers de Telecomunicació es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica es_ES
dc.description.bibliographicCitation Alfonso Gil, JC.; Vague Cardona, JJ.; Orts-Grau, S.; Gimeno Sales, FJ.; Segui-Chilet, S. (2013). Enhanced Grid Fundamental Positive-Sequence Digital Synchronization Structure. IEEE Transactions on Power Delivery. 28(1):226-234. doi:10.1109/TPWRD.2012.2219559 es_ES
dc.description.accrualMethod S es_ES
dc.relation.publisherversion http://dx.doi.org/10.1109/TPWRD.2012.2219559 es_ES
dc.description.upvformatpinicio 226 es_ES
dc.description.upvformatpfin 234 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 28 es_ES
dc.description.issue 1 es_ES
dc.relation.senia 260380 es_ES
dc.identifier.eissn 1937-4208


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