Design of a Wormhole Switching Router

Abstract

Nowadays chips consist in so many system inside a chip se we will need to study different options to communicate them. It is useful to have a view of how a specific router architecture can work so my original contribution to knowledge is a design and a test of a wormhole router. We will need to specify a router to design, design it and test it. We will have a look at the different modules that compose, and how the specifications become hardware. As we want that router to be able to translate to a chip architecture to design the router synthesizable VHDL will be used. Complexity data of the router will be extracted from the synthesis in a Xilinx fpga. Once the router is fully finished, a test bed will be created to test the router in under 3 different traffic patterns: URT, LTR, and HST. Using Matlab and the data extracted from the simulation we will find out the value of blocking rate and the latency for various levels of traffic. Those two metrics will characterise the behaviour of this router in different situations. And will show what we could expect from a router like that, a better behaviour in a mesh with no central nodes. The router has been proven to be synthesizable in an fpga. To finish this router will be compared to another wormhole router called CRATE to find out the strengths of this design