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dc.contributor.author | Sahuquillo Borrás, Julio | es_ES |
dc.contributor.author | Hassan Mohamed, Houcine | es_ES |
dc.contributor.author | Petit Martí, Salvador Vicente | es_ES |
dc.contributor.author | March Cabrelles, José Luis | es_ES |
dc.contributor.author | Duato Marín, José Francisco | es_ES |
dc.date.accessioned | 2017-05-18T12:17:24Z | |
dc.date.available | 2017-05-18T12:17:24Z | |
dc.date.issued | 2016-03 | |
dc.identifier.issn | 0167-739X | |
dc.identifier.uri | http://hdl.handle.net/10251/81399 | |
dc.description | this is the author’s version of a work that was accepted for publication in Future Generation Computer Systems. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in Future Generation Computer Systems, vol. 56 (2016). DOI 10.1016/j.future.2015.06.011. | es_ES |
dc.description.abstract | Nowadays, real-time embedded applications have to cope with an increasing demand of functionalities, which require increasing processing capabilities. With this aim real-time systems are being implemented on top of high-performance multicore processors that run multithreaded periodic workloads by allocating threads to individual cores. In addition, to improve both performance and energy savings, the industry is introducing new multicore designs such as ARM’s big.LITTLE that include heterogeneous cores in the same package. A key issue to improve energy savings in multicore embedded real-time systems and reduce the number of deadline misses is to accurately estimate the execution time of the tasks considering the supported processor frequencies. Two main aspects make this estimation difficult. First, the running threads compete among them for shared resources. Second, almost all current microprocessors implement Dynamic Voltage and Frequency Scaling (DVFS) regulators to dynamically adjust the voltage/frequency at run-time according to the workload behavior. Existing execution time estimation models rely on off-line analysis or on the assumption that the task execution time scales linearly with the processor frequency, which can bring important deviations since the memory system uses a different power supply. In contrast, this paper proposes the Processor–Memory (Proc–Mem) model, which dynamically predicts the distinct task execution times depending on the implemented processor frequencies. A power-aware EDF (Earliest Deadline First)-based scheduler using the Proc–Mem approach has been evaluated and compared against the same scheduler using a typical Constant Memory Access Time model, namely CMAT. Results on a heterogeneous multicore processor show that the average deviation of Proc–Mem is only by 5.55% with respect to the actual measured execution time, while the average deviation of the CMAT model is 36.42%. These results turn in important energy savings, by 18% on average and up to 31% in some mixes, in comparison to CMAT for a similar number of deadline misses. © 2015 Elsevier B.V. All rights reserved. | es_ES |
dc.description.sponsorship | This work was supported by the Spanish Ministerio de Economia y Competitividad (MINECO) and by FEDER funds under Grant TIN2012-38341-004-01, and by the Intel Early Career Faculty Honor Program Award. | en_EN |
dc.language | Inglés | es_ES |
dc.publisher | Elsevier | es_ES |
dc.relation.ispartof | Future Generation Computer Systems | es_ES |
dc.rights | Reserva de todos los derechos | es_ES |
dc.subject | Heterogeneous multicore architectures | es_ES |
dc.subject | Time predictable multicore architectures | es_ES |
dc.subject | Time aware energy efficiency | es_ES |
dc.subject | Energy savings | es_ES |
dc.subject | Real-time embedded systems | es_ES |
dc.subject.classification | ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES | es_ES |
dc.title | A dynamic execution time estimation model to save energy in heterogeneous multicores running periodic tasks | es_ES |
dc.type | Artículo | es_ES |
dc.identifier.doi | 10.1016/j.future.2015.06.011 | |
dc.relation.projectID | info:eu-repo/grantAgreement/MINECO//TIN2012-38341-C04-01/ES/MEJORA DE LA ARQUITECTURA DE SERVIDORES, SERVICIOS Y APLICACIONES/ | es_ES |
dc.rights.accessRights | Abierto | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Escola Tècnica Superior d'Enginyeria Informàtica | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Escuela Técnica Superior de Ingeniería del Diseño - Escola Tècnica Superior d'Enginyeria del Disseny | es_ES |
dc.description.bibliographicCitation | Sahuquillo Borrás, J.; Hassan Mohamed, H.; Petit Martí, SV.; March Cabrelles, JL.; Duato Marín, JF. (2016). A dynamic execution time estimation model to save energy in heterogeneous multicores running periodic tasks. Future Generation Computer Systems. 56:211-219. https://doi.org/10.1016/j.future.2015.06.011 | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.publisherversion | http://dx.doi.org/10.1016/j.future.2015.06.011 | es_ES |
dc.description.upvformatpinicio | 211 | es_ES |
dc.description.upvformatpfin | 219 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.description.volume | 56 | es_ES |
dc.relation.senia | 333265 | es_ES |
dc.contributor.funder | Ministerio de Economía y Competitividad | es_ES |