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dc.contributor.author | Bermúdez Garzón, Diego Fernando | es_ES |
dc.contributor.author | Gómez Requena, Crispín | es_ES |
dc.contributor.author | Gómez Requena, María Engracia | es_ES |
dc.contributor.author | López Rodríguez, Pedro Juan | es_ES |
dc.contributor.author | Duato Marín, José Francisco | es_ES |
dc.date.accessioned | 2017-06-14T08:06:06Z | |
dc.date.available | 2017-06-14T08:06:06Z | |
dc.date.issued | 2016-04 | |
dc.identifier.issn | 1045-9219 | |
dc.identifier.uri | http://hdl.handle.net/10251/82819 | |
dc.description | © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |
dc.description.abstract | On the one hand, performance and fault-tolerance of interconnection networks are key design issues for high performance computing (HPC) systems. On the other hand, cost should be also considered. Indirect topologies are often chosen in the design of HPC systems. Among them, the most commonly used topology is the fat-tree. In this work, we focus on getting the maximum benefits from the network resources by designing a simple indirect topology with very good performance and fault-tolerance properties, while keeping the hardware cost as low as possible. To do that, we propose some extensions to the fat-tree topology to take full advantage of the hardware resources consumed by the topology. In particular, we propose three new topologies with different properties in terms of cost, performance and fault-tolerance. All of them are able to achieve a similar or better performance results than the fat-tree, providing also a good level of fault-tolerance and, contrary to most of the available topologies, these proposals are able to tolerate also faults in the links that connect to end nodes. | es_ES |
dc.description.sponsorship | This work was supported by the Spanish Ministerio de Economia y Competitividad (MINECO) and by FEDER funds under Grant TIN2012-38341-C04-01. | en_EN |
dc.language | Inglés | es_ES |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | es_ES |
dc.relation.ispartof | IEEE Transactions on Parallel and Distributed Systems | es_ES |
dc.rights | Reserva de todos los derechos | es_ES |
dc.subject | Regular Indirect Topologies | es_ES |
dc.subject | Fat-Trees | es_ES |
dc.subject | Adaptive and Deterministic Routing | es_ES |
dc.subject | RUFT | es_ES |
dc.subject | Fault Tolerance | es_ES |
dc.subject.classification | ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES | es_ES |
dc.title | A Family of Fault-Tolerant Efficient Indirect Topologies | es_ES |
dc.type | Artículo | es_ES |
dc.identifier.doi | 10.1109/TPDS.2015.2430863 | |
dc.relation.projectID | info:eu-repo/grantAgreement/MINECO//TIN2012-38341-C04-01/ES/MEJORA DE LA ARQUITECTURA DE SERVIDORES, SERVICIOS Y APLICACIONES/ | es_ES |
dc.rights.accessRights | Abierto | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Escola Tècnica Superior d'Enginyeria Informàtica | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Instituto Universitario de Aplicaciones de las Tecnologías de la Información - Institut Universitari d'Aplicacions de les Tecnologies de la Informació | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors | es_ES |
dc.description.bibliographicCitation | Bermúdez Garzón, DF.; Gómez Requena, C.; Gómez Requena, ME.; López Rodríguez, PJ.; Duato Marín, JF. (2016). A Family of Fault-Tolerant Efficient Indirect Topologies. IEEE Transactions on Parallel and Distributed Systems. 27(4):927-940. https://doi.org/10.1109/TPDS.2015.2430863 | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/7103363/ | es_ES |
dc.description.upvformatpinicio | 927 | es_ES |
dc.description.upvformatpfin | 940 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.description.volume | 27 | es_ES |
dc.description.issue | 4 | es_ES |
dc.relation.senia | 294848 | es_ES |
dc.contributor.funder | Ministerio de Economía y Competitividad | es_ES |