Sansaloni Balaguer, Trinidad Mª
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- PublicationModifed Shuffled Based Architecture for High Throughput Decoding of LDPC Codes(Springer Verlag (Germany), 2012-08) Angarita, Fabián; Sansaloni Balaguer, Trinidad Mª; Pérez Pascual, Mª Asunción; Valls Coquillat, Javier; Departamento de Ingeniería Electrónica; Instituto Universitario de Telecomunicación y Aplicaciones Multimedia; Escuela Politécnica Superior de Gandia; Ministerio de Ciencia e InnovaciónLow Density Parity-Check (LDPC) codes achieve the best performance when they are decoded with the sum-product (SP) algorithm. This is a two-phase iterative algorithm where two types of messages are interchanged and updated in each iteration. The group-shuffled or layered decoding schemes applied to the SP algorithm speed up its convergence by modifying its schedule, so they yield a reduction in the number of iterations required to achieve a given performance. However, the two-phase processing is still maintained. In this paper a modification of the group-shuffled scheme suitable for high-rate LDPC codes is proposed. The modification allows the overlapping of the two-phase computation, achieving a convergence speed up close to that of the group-shuffled scheme with higher throughput. Besides, high throughput architectures are presented for the modified algorithm. As an example, the proposed architecture has been implemented for the 2048-bit LDPC code of the IEEE 802.3an standard and it was synthesized in a 90 nm CMOS process achieving a throughput of 22.40 Gbps at 14 iterations with a clock frequency of 306 MHz and a total area of 10.5 mm(2). Furthermore, the decoder performs within 0.5 dB of the floating-point 100 iterations sum-product algorithm at a PER of 10(-5).
- PublicationImproved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes(Springer Verlag (Germany), 2012-02) Angarita Preciado, Fabián Enrique; Sansaloni Balaguer, Trinidad Mª; Canet Subiela, María José; Valls Coquillat, Javier; Departamento de Ingeniería Electrónica; Instituto Universitario de Telecomunicación y Aplicaciones Multimedia; Escuela Politécnica Superior de Gandia; Ministerio de Ciencia e Innovación; European Regional Development FundThis paper presents an architecture for high-throughput decoding of high-rate Low-Density Parity-Check (LDPC) codes. The proposed architecture is a modification of the sliced message passing (SMP) decoding architecture which overlaps the check-node and variable-node update stages, achieving a good tradeoff between area and throughput, and also, high hardware utilization efficiency (HUE). The proposed modification does not affect the performance of the SMP algorithm and yields an area reduction of 33%. As an example, SMP architecture and the proposed modification was synthesized in a 90 nm CMOS process for the 2048-bit LDPC code of the IEEE802.3an standard with 16 iterations achieving a throughput of 5.9 Gbps with 15.3 mm2 and 6.2 Gbps with 10.2 mm2, respectively.