Valls Coquillat, Javier
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- PublicationModifed Shuffled Based Architecture for High Throughput Decoding of LDPC Codes(Springer Verlag (Germany), 2012-08) Angarita, Fabián; Sansaloni Balaguer, Trinidad Mª; Pérez Pascual, Mª Asunción; Valls Coquillat, Javier; Departamento de Ingeniería Electrónica; Instituto Universitario de Telecomunicación y Aplicaciones Multimedia; Escuela Politécnica Superior de Gandia; Ministerio de Ciencia e InnovaciónLow Density Parity-Check (LDPC) codes achieve the best performance when they are decoded with the sum-product (SP) algorithm. This is a two-phase iterative algorithm where two types of messages are interchanged and updated in each iteration. The group-shuffled or layered decoding schemes applied to the SP algorithm speed up its convergence by modifying its schedule, so they yield a reduction in the number of iterations required to achieve a given performance. However, the two-phase processing is still maintained. In this paper a modification of the group-shuffled scheme suitable for high-rate LDPC codes is proposed. The modification allows the overlapping of the two-phase computation, achieving a convergence speed up close to that of the group-shuffled scheme with higher throughput. Besides, high throughput architectures are presented for the modified algorithm. As an example, the proposed architecture has been implemented for the 2048-bit LDPC code of the IEEE 802.3an standard and it was synthesized in a 90 nm CMOS process achieving a throughput of 22.40 Gbps at 14 iterations with a clock frequency of 306 MHz and a total area of 10.5 mm(2). Furthermore, the decoder performs within 0.5 dB of the floating-point 100 iterations sum-product algorithm at a PER of 10(-5).
- PublicationHigh-Performance NB-LDPC Decoder With Reduction of Message Exchange(Institute of Electrical and Electronics Engineers (IEEE), 2016-05) Lacruz, Jesus O.; García Herrero, Francisco Miguel; Canet Subiela, María José; Valls Coquillat, Javier; Departamento de Ingeniería Electrónica; Instituto Universitario de Telecomunicación y Aplicaciones Multimedia; Escuela Politécnica Superior de Gandia; Generalitat Valenciana; Ministerio de Economía y Competitividad; Ministerio de Ciencia e InnovaciónThis paper presents a novel algorithm based on trellis min-max for decoding non-binary low-density parity-check (NB-LDPC) codes. This decoder reduces the number of messages exchanged between check node and variable node processors, which decreases the storage resources and the wiring congestion and, thus, increases the throughput of the decoder. Our frame error rate performance simulations show that the proposed algorithm has a negligible performance loss for high-rate codes with GF(16) and GF(32), and a performance loss smaller than 0.07 dB for high-rate codes over GF(64). In addition, a layered decoder architecture is presented and implemented on a 90-nm CMOS process for the following high-rate NB-LDPC codes: (2304, 2048) over GF(16), (837, 726) over GF(32), and (1536, 1344) over GF(64). In all cases, the achieved throughput is higher than 1 Gb/s.
- PublicationFPGA implementation of an OFDM-based WLAN receiver(Elsevier, 2012-05) Canet Subiela, María José; Valls Coquillat, Javier; Almenar Terré, Vicenç; Marín-Roig Ramón, José; Departamento de Ingeniería Electrónica; Departamento de Comunicaciones; Instituto Universitario de Telecomunicación y Aplicaciones Multimedia; Escuela Politécnica Superior de Gandia; Ministerio de Ciencia e InnovaciónThis paper deals with the design and implementation on FPGA of a receiver for OFDM-based WLAN. The circuit is particularized for IEEE 802.11a/g standards. The system includes frame detection, time and frequency synchronization, demodulation, equalization and phase tracking. The algorithms to be implemented for each task are selected taking into account performance, hardware cost and latency. Also, a fixed point analysis is made for each algorithm. Our objective is to maintain the PER loss below 0.5 dB for a PER = 10 -2, 64-QAM and error correction. The whole system is composed of two main blocks (correlator and CORDIC) that are reused in different time intervals to perform all the necessary operations, so the required hardware resources are minimized. To verify it, the receiver is physically implemented and tested. © 2011 Elsevier B.V. All rights reserved.
- PublicationNon-binary LDPC decoder based on symbol flipping with multiple votes(Institute of Electrical and Electronics Engineers (IEEE), 2014-05) García Herrero, Francisco Miguel; Declercq, D.; Valls Coquillat, Javier; Departamento de Ingeniería Electrónica; Instituto Universitario de Telecomunicación y Aplicaciones Multimedia; Escuela Politécnica Superior de Gandia; Ministerio de Ciencia e Innovación; Ministerio de Educación; Institut Universitaire de FranceIn this letter, a new algorithm to decode non-binary LDPC (NB-LDPC) codes is proposed. This algorithm is inspired from very low complexity decoders that have been proposed recently, in which only syndrome computations at the check node update are used, while performing symbol-flipping based update at the variable node. Usually, the low complexity decoders based on symbol flipping suffer from a non-negligible performance degradation compared to soft-decision NB-LDPC decoders. Our improved decoder makes use of a list of syndrome computations instead of a single one based on hard-decision, and builds soft information at the variable node input by assigning votes weighted by different amplitudes. Simulations show that using multiple votes with multiple weights yields better performance, while still maintaining the low complexity feature.
- PublicationFast- and Low-Complexity atan2(a,b) Approximation(Institute of Electrical and Electronics Engineers, 2017) Torres Carot, Vicente; Valls Coquillat, Javier; Lyons, Richard; Departamento de Ingeniería Electrónica; Escuela Técnica Superior de Ingeniería de Telecomunicación; Instituto Universitario de Telecomunicación y Aplicaciones Multimedia; Escuela Politécnica Superior de Gandia; Ministerio de Economía, Industria y Competitividad; European Regional Development Fund[EN] This article presents a new entry to the class of published algorithms for the fast computation of the arctangent of a complex number. Our method uses a look-up table (LUT) to reduce computational errors. We also show how to convert a large-sized LUT addressed by two variables to an equivalent-performance smaller-sized LUT addressed by only one variable. In addition, we demonstrate how and why the use of follow-on LUTs applied to other simple arctan algorithms produce unexpected and interesting results.
- PublicationReal-time 20.37 Gb/s optical OFDM receiver for PON IM/DD systems(The Optical Society, 2018) Bruno, Julian Santiago; Almenar Terré, Vicenç; Valls Coquillat, Javier; Corral González, Juan Luis; Departamento de Ingeniería Electrónica; Departamento de Comunicaciones; Instituto Universitario de Telecomunicación y Aplicaciones Multimedia; Instituto Universitario de Tecnología Nanofotónica; Escuela Politécnica Superior de Gandia; Ministerio de Economía, Industria y Competitividad[EN] This paper presents the hardware architecture of an OFDM receiver suitable for optical communications. The receiver has been implemented in an FPGA device and used to demonstrate experimentally an optical OFDM transmission in a passive optical link with a directly modulated DFB laser and DAC/ADC at 5 GS/s. A bit rate of 20.37 Gb/s is achieved using an OFDM signal with subcarrier modulation format up to 512-QAM, it has been successfully transmitted over 10 km SSMF with a spectral efficiency of 8.38 bit/s/Hz.
- PublicationSoft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code(MDPI AG, 2019-01) Torres Carot, Vicente; Valls Coquillat, Javier; Canet Subiela, María José; García Herrero, Francisco Miguel; Departamento de Ingeniería Electrónica; Escuela Técnica Superior de Ingeniería de Telecomunicación; Instituto Universitario de Telecomunicación y Aplicaciones Multimedia; Escuela Politécnica Superior de Gandia; European Regional Development Fund; Ministerio de Economía y Competitividad[EN] In this work, we present a new architecture for soft-decision Reed-Solomon (RS) Low-Complexity Chase (LCC) decoding. The proposed architecture is scalable and can be used for a high number of test vectors. We propose a novel Multiplicity Assignment stage that sorts and stores only the location of the errors inside the symbols and the powers of a that identify the positions of the symbols in the frame. Novel schematics for the Syndrome Update and Symbol Modification blocks that are adapted to the proposed sorting stage are also presented. We also propose novel solutions for the problems that arise when a high number of test vectors is processed. We implemented three decoders: a h = 4 LCC decoder and two decoders that only decode 31 and 60 test vectors of true h = 5 and h = 6 LCC decoders, respectively. For example, our h = 4 decoder requires 29% less look-up tables in Virtex-V Field Programmable Gate Array (FPGA) devices than the best soft-decision RS decoder published to date, while has a 0.07 dB coding gain over that decoder.
- PublicationReduced-complexity min-sum algorithm for decoding LDPC codes with low error-floor(Institute of Electrical and Electronics Engineers (IEEE), 2014-07) Angarita, Fabián; Valls Coquillat, Javier; Almenar Terré, Vicenç; Torres Carot, Vicente; Departamento de Ingeniería Electrónica; Escuela Técnica Superior de Ingeniería de Telecomunicación; Departamento de Comunicaciones; Instituto Universitario de Telecomunicación y Aplicaciones Multimedia; Escuela Politécnica Superior de Gandia; Ministerio de Ciencia e Innovación; Ministerio de Economía y CompetitividadThis paper proposes a low-complexity min-sum algorithm for decoding low-density parity-check codes. It is an improved version of the single-minimum algorithm where the two-minimum calculation is replaced by one minimum calculation and a second minimum emulation. In the proposed one, variable correction factors that depend on the iteration number are introduced and the second minimum emulation is simplified, reducing by this way the decoder complexity. This proposal improves the performance of the single-minimum algorithm, approaching to the normalized min-sum performance in the water-fall region. Also, the error-floor region is analyzed for the code of the IEEE 802.3an standard showing that the trapping sets are decoded due to a slow down of the convergence of the algorithm. An error-floor free operation below BER = 10(-15) is shown for this code by means of a field-programmable gate array (FPGA)-based hardware emulator. A layered decoder is implemented in a 90-nm CMOS technology achieving 12.8 Gbps with an area of 3.84 mm(2)
- PublicationLinear Response Modeling of High Luminous Flux Phosphor-Coated White LEDs for VLC(Institute of Electrical and Electronics Engineers, 2022-06-15) Salvador Llàcer, Pau; Valls Coquillat, Javier; Corral González, Juan Luis; Almenar Terré, Vicenç; Canet Subiela, María José; Departamento de Ingeniería Electrónica; Departamento de Comunicaciones; Instituto Universitario de Telecomunicación y Aplicaciones Multimedia; Instituto Universitario de Tecnología Nanofotónica; Escuela Politécnica Superior de Gandia; Instituto de Instrumentación para Imagen Molecular; AGENCIA ESTATAL DE INVESTIGACION; MINISTERIO DE UNIVERSIDADES E INVESTIGACION[EN] The widespread deployment of LEDs for illumination purposes has open the door to the use of these devices for visible light communications (VLC). Most lighting fixtures are mounted with phosphor-based white LEDs, and a driver connected to the LED is also required for VLC. This paper shows that the parasitic effects introduced by this setup change the frequency response of the intrinsic LED. A linear model to characterize the whole setup is proposed, as well as a methodology to extract its parameters. This methodology allows the designer to characterize the frequency response of LEDs without the additional difficulty of knowing the specific parasitic components introduced by the setup. The proposed model offers an accurate estimation of the slope of the LED frequency response in order to broaden the frequency range in which the model is useful to characterize and simulate VLC links. This was corroborated with the characterization of three commercial white LEDs whose measured and modeled frequency responses matched perfectly.
- PublicationA Fast and Low-Complexity Operator for the Computation of the Arctangent of a Complex Number(Institute of Electrical and Electronics Engineers, 2017) Torres Carot, Vicente; Valls Coquillat, Javier; Departamento de Ingeniería Electrónica; Escuela Técnica Superior de Ingeniería de Telecomunicación; Instituto Universitario de Telecomunicación y Aplicaciones Multimedia; Escuela Politécnica Superior de Gandia; Ministerio de Economía, Industria y Competitividad[EN] The computation of the arctangent of a complex number, i.e., the atan2 function, is frequently needed in hardware systems that could profit from an optimized operator. In this brief, we present a novel method to compute the atan2 function and a hardware architecture for its implementation. The method is based on a first stage that performs a coarse approximation of the atan2 function and a second stage that improves the output accuracy by means of a lookup table. We present results for fixed-point implementations in a field-programmable gate array device, all of them guaranteeing last-bit accuracy, which provide an advantage in latency, speed, and use of resources, when compared with well-established fixed-point options.