Multiple-vote symbol flipping decoder for non-binary LDPC codes

dc.contributor.affiliationDepartamento de Ingeniería Electrónica
dc.contributor.affiliationInstituto Universitario de Telecomunicación y Aplicaciones Multimedia
dc.contributor.affiliationEscuela Politécnica Superior de Gandia
dc.contributor.authorGarcía Herrero, Francisco Migueles_ES
dc.contributor.authorLi, Erbaoes_ES
dc.contributor.authorDeclercq, Davides_ES
dc.contributor.authorValls Coquillat, Javier
dc.contributor.funderMinisterio de Ciencia e Innovaciónes_ES
dc.contributor.funderUniversitat Politècnica de Valènciaes_ES
dc.contributor.funderMinisterio de Educaciónes_ES
dc.contributor.funderInstitut Universitaire de Francees_ES
dc.date.accessioned2015-06-29T16:31:13Z
dc.date.available2015-06-29T16:31:13Z
dc.date.issued2014-11
dc.description.abstractA multiple-vote symbol-flipping (MV-SF) decoding algorithm for nonbinary low-density parity-check (NB-LDPC) codes is proposed in this paper. Our algorithm improves the generalized bit-flipping algorithm (GBFDA) by considering the multiplicity of the candidates at the check-node output, to perform a more accurate symbol-flipping decision at the variable node update. The MV-SF algorithm greatly improves the frame error rate performance of GBFDA and approaches the performance of the best state-of-the-art decoders [extended min-sum and min-max (Min-Max)] with lower complexity. For a (N = 837, K = 723) NB-LDPC code over GF(32), the decoder derived from the proposed algorithm can reach a throughput higher than 500 Mb/s and a coding gain of 0.44 dB compared with the most efficient GBFDA architecture with only twice the silicon area. Our architecture has 27% efficiency gain compared with the best Min-Max architecture found in the literature, with a performance loss of just 0.21 dB at frame error rate 10(-4)es_ES
dc.description.accrualMethodSes_ES
dc.description.bibliographicCitationGarcía Herrero, FM.; Li, E.; Declercq, D.; Valls Coquillat, J. (2014). Multiple-vote symbol flipping decoder for non-binary LDPC codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22(11):2256-2267. https://doi.org/10.1109/TVLSI.2013.2292900es_ES
dc.description.issue11es_ES
dc.description.sponsorshipThis work was supported in part by the Spanish Ministerio de Ciencia e Innovacion under Grant TEC2011-27916, in part by the Universitat Politecnica de Valencia under Grant SP20120625, and in part by the Institut Universitaire de France. The work of F. Garcia-Herrero was supported by the Spanish Government, Ministerio de Educacion, under Grant AP2010-5178.en_EN
dc.description.upvformatpfin2267es_ES
dc.description.upvformatpinicio2256es_ES
dc.description.volume22es_ES
dc.identifier.doi10.1109/TVLSI.2013.2292900
dc.identifier.issn1063-8210
dc.identifier.urihttps://riunet.upv.es/handle/10251/52446
dc.languageIngléses_ES
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)es_ES
dc.relation.ispartofIEEE Transactions on Very Large Scale Integration (VLSI) Systemses_ES
dc.relation.projectIDinfo:eu-repo/grantAgreement/MICINN//TEC2011-27916/ES/ALGORITMOS Y ARQUITECTURAS DE FEC PARA FUTUROS SISTEMAS DE COMUNICACIONES/es_ES
dc.relation.projectIDinfo:eu-repo/grantAgreement/UPV//SP20120625/es_ES
dc.relation.projectIDinfo:eu-repo/grantAgreement/ME//AP2010-5178/ES/AP2010-5178/es_ES
dc.relation.publisherversionhttp://dx.doi.org/10.1109/TVLSI.2013.2292900es_ES
dc.relation.senia283754
dc.rightsReserva de todos los derechoses_ES
dc.rights.accessRightsCerradoes_ES
dc.subjectDecodinges_ES
dc.subjectError correction codeses_ES
dc.subjectInformation theoryes_ES
dc.subjectIterative decodinges_ES
dc.subject.classificationTECNOLOGIA ELECTRONICAes_ES
dc.titleMultiple-vote symbol flipping decoder for non-binary LDPC codeses_ES
dc.typeArtículoes_ES
dc.type.versioninfo:eu-repo/semantics/publishedVersiones_ES
dspace.entity.typePublication
person.identifier4173
person.identifier.orcid0000-0002-9390-5022
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relation.isAuthorOfPublication.latestForDiscovery9b2e27eb-936e-4691-884c-fda1116f2786
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