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Ravenscar Support for Time-Triggered Scheduling

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Ravenscar Support for Time-Triggered Scheduling

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dc.contributor.author Real Sáez, Jorge Vicente es_ES
dc.contributor.author Sáez Barona, Sergio es_ES
dc.contributor.author Crespo, Alfons es_ES
dc.date.accessioned 2019-05-31T20:44:05Z
dc.date.available 2019-05-31T20:44:05Z
dc.date.issued 2018 es_ES
dc.identifier.issn 1094-3641 es_ES
dc.identifier.uri http://hdl.handle.net/10251/121375
dc.description.abstract [EN] This position paper follows from a previous proposal to integrate a time-triggered scheduler in a prioritybased, preemptive scheduler such as that supported by Ada¿s task dispatching policy FIFO Within Priorities . The resulting combined scheduling carries the advantages of both time-triggered and priority-based scheduling, and helps mitigating their drawbacks. The paper presents a system model for the time-triggered subsystem that extends the original proposal, and describes a Ravenscar implementation of the scheduler at the run-time system level, in the form of a new package Ada.Dispatching.TTS. Multiple programming patterns can be implemented on top of this scheduler. With respect to the previously proposed full-Ada implementation, only patterns that implied the use of asynchronous transfer of control have been excluded. On the other hand, the extension of the original model enables new patterns, not supported in our previous proposal, using the new types of continuation and optional slots. We hold that bringing the time-triggered paradigm to Ravenscar is both feasible and convenient for the High-Integrity and Embedded application domains. es_ES
dc.description.sponsorship This work has been partly supported by the Spanish Government’s project M2C2 (TIN2014-56158-C4-1-P-AR) and the European Commission’s projects ENABLE-S3 and AQUAS (ECSEL-JU, Contracts 692455 and 737475)
dc.language Inglés es_ES
dc.publisher Association for Computing Machinery es_ES
dc.relation.ispartof ACM SIGAda Ada Letters es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject Real-Time Systems es_ES
dc.subject Time-Triggered Scheduling es_ES
dc.subject Priority-Based Scheduling es_ES
dc.subject Ravenscar Profile es_ES
dc.subject High-Integrity Systems es_ES
dc.subject Embedded Systems es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.title Ravenscar Support for Time-Triggered Scheduling es_ES
dc.type Artículo es_ES
dc.identifier.doi 10.1145/3241950.3241957 es_ES
dc.relation.projectID info:eu-repo/grantAgreement/EC/H2020/692455/EU/European Initiative to Enable Validation for Highly Automated Safe and Secure Systems/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/MINECO//TIN2014-56158-C4-1-P/ES/SISTEMAS CIBER-FISICOS DE CRITICIDAD MIXTA SOBRE PLATAFORMAS MULTINUCLEO/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/EC/H2020/737475/EU/Aggregated Quality Assurance for Systems/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/MINECO//ECS-010000-2015-24/ es_ES
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.description.bibliographicCitation Real Sáez, JV.; Sáez Barona, S.; Crespo, A. (2018). Ravenscar Support for Time-Triggered Scheduling. ACM SIGAda Ada Letters. 38(1):41-54. https://doi.org/10.1145/3241950.3241957 es_ES
dc.description.accrualMethod S es_ES
dc.relation.publisherversion http://doi.org/10.1145/3241950.3241957 es_ES
dc.description.upvformatpinicio 41 es_ES
dc.description.upvformatpfin 54 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 38 es_ES
dc.description.issue 1 es_ES
dc.relation.pasarela S\384010 es_ES
dc.contributor.funder European Commission es_ES
dc.contributor.funder Ministerio de Economía y Competitividad es_ES
dc.description.references M. Aldea and M. González-Harbour. MaRTE OS: An Ada Kernel for Real-Time Embedded Applications. Reliable Software Technologies - Ada Europe 2001, Lecture Notes in Computer Science, 2043:305-316, 2001. es_ES
dc.description.references ISO/IEC-JTC1-SC22-WG9. Ada Reference Manual ISO/IEC 8652:2012(E). URL: http://www.ada-europe.org/manuals/LRM-2012.pdf, 2012. es_ES
dc.description.references J. Leung and J. Whitehead. On the complexity of xed-priority scheduling of periodic, real-time tasks. Performance Evaluation (Netherlands), 2(4):237-250, 1982. es_ES
dc.description.references C. Liu and J. Layland. Scheduling Algorithms for Multiprogramming in a Hard Real-Time Environment. Journal of the ACM, 20(1):46-61, 1973. es_ES
dc.description.references J. Real and P. Rogers. Session Summary: Experience. Ada Letters, 36(1):101-102, June 2016. es_ES
dc.description.references J. Real, S. Sáez, and A. Crespo. Combined scheduling of time-triggeed plans and priority scheduled task sets. Ada Letters, 36(1):68-76, June 2016. es_ES
dc.description.references J. Real, S. Sáez, and A. Crespo. Combining time-triggered plans with priority scheduled task sets. In M. Bertogna and L. M. Pinho, editors, Reliable Software Technologies - Ada-Europe 2016, volume 9695 of Lecture Notes in Computer Science. Springer, June 2016. es_ES
dc.description.references S. Sáez and J. Real. TTS Ravenscar runtime. https://doi.org/10.5281/zenodo.1168723, February 2018. es_ES


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