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dc.contributor.author | Feliu-Pérez, Josué | es_ES |
dc.contributor.author | Sahuquillo Borrás, Julio | es_ES |
dc.contributor.author | Petit Martí, Salvador Vicente | es_ES |
dc.date.accessioned | 2019-06-07T20:04:34Z | |
dc.date.available | 2019-06-07T20:04:34Z | |
dc.date.issued | 2018 | es_ES |
dc.identifier.issn | 0743-7315 | es_ES |
dc.identifier.uri | http://hdl.handle.net/10251/121757 | |
dc.description.abstract | [EN] Computer architecture courses typically include lab sessions to reinforce, from a practical perspective, concepts and architectural mechanisms studied in lectures. Lab sessions are mainly based on simulation frameworks because they benefit learning. Reading the source code that models certain processor mechanisms allows students to acquire a sound knowledge of how hardware works. Unfortunately, simulators that model current multicore processors are getting more and more complex, which lengthens the learning phase and complicates their use in time-bounded lab sessions. In this paper, we propose a new approach that complements the use of simulation frameworks in lab sessions of computer architecture courses. This approach is based on performing experiments on current commercial processors, where multiple hardware events related to the performance of the computer components under study are monitored. Then, students analyze the measured events and how they impact the overall performance. Such analysis motivates students and, not only helps reinforcing the theoretical concepts, but also increases their analysis skills. In this paper we present the methodology and scheduling framework that support the proposed approach and discuss five lab sessions, which can be applied in different courses, covering multiple computer architecture topics. (C) 2018 Elsevier Inc. All rights reserved. | es_ES |
dc.description.sponsorship | Josue Feliu has been partially supported through a postdoctoral fellowship by the Generalitat Valenciana (APOSTD/2017/052). Additional support has been provided by the Spanish Ministerio de Economia y Competitividad (MINECO) and Plan E funds, under grants TIN2015-66972-C5-1-R and TIN2014-62246-EXP. | es_ES |
dc.language | Inglés | es_ES |
dc.publisher | Elsevier | es_ES |
dc.relation.ispartof | Journal of Parallel and Distributed Computing | es_ES |
dc.rights | Reconocimiento - No comercial - Sin obra derivada (by-nc-nd) | es_ES |
dc.subject | Lab sessions | es_ES |
dc.subject | Computer architecture | es_ES |
dc.subject | Real processors | es_ES |
dc.subject | Processor complexity | es_ES |
dc.subject | Scheduling framework | es_ES |
dc.subject.classification | ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES | es_ES |
dc.title | Designing lab sessions focusing on real processors for computer architecture courses: A practical perspective | es_ES |
dc.type | Artículo | es_ES |
dc.type | Comunicación en congreso | es_ES |
dc.identifier.doi | 10.1016/j.jpdc.2018.02.026 | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/GVA//APOSTD%2F2017%2F052/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/MINECO//TIN2014-62246-EXP/ES/CODISEÑO HARDWARE-SOFTWARE PARA PLANIFICACION EQUITATIVA EN PROCESADORES SMT MULTINUCLEO/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/MINECO//TIN2015-66972-C5-1-R/ES/TECNICAS PARA LA MEJORA DE LAS PRESTACIONES, COSTE Y CONSUMO DE ENERGIA DE LOS SERVIDORES/ | es_ES |
dc.rights.accessRights | Abierto | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors | es_ES |
dc.description.bibliographicCitation | Feliu-Pérez, J.; Sahuquillo Borrás, J.; Petit Martí, SV. (2018). Designing lab sessions focusing on real processors for computer architecture courses: A practical perspective. Journal of Parallel and Distributed Computing. 118:128-139. https://doi.org/10.1016/j.jpdc.2018.02.026 | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.conferencename | Workshop on Education for High-Performance Computing (EduHPC-16) | es_ES |
dc.relation.conferencedate | Noviembre 13-18,2016 | es_ES |
dc.relation.conferenceplace | Salt Lake, USA | es_ES |
dc.relation.publisherversion | http://doi.org/10.1016/j.jpdc.2018.02.026 | es_ES |
dc.description.upvformatpinicio | 128 | es_ES |
dc.description.upvformatpfin | 139 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.description.volume | 118 | es_ES |
dc.relation.pasarela | S\361931 | es_ES |
dc.contributor.funder | Generalitat Valenciana | es_ES |
dc.contributor.funder | Ministerio de Economía, Industria y Competitividad | es_ES |