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Fault Modeling of Graphene Nanoribbon FET Logic Circuits

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Fault Modeling of Graphene Nanoribbon FET Logic Circuits

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dc.contributor.author Gil Tomás, Daniel Antonio es_ES
dc.contributor.author Gracia-Morán, Joaquín es_ES
dc.contributor.author Saiz-Adalid, Luis-J. es_ES
dc.contributor.author Gil, Pedro es_ES
dc.date.accessioned 2020-06-02T05:36:54Z
dc.date.available 2020-06-02T05:36:54Z
dc.date.issued 2019-07-31 es_ES
dc.identifier.uri http://hdl.handle.net/10251/144807
dc.description.abstract [EN] Due to the increasing defect rates in highly scaled complementary metal-oxide-semiconductor (CMOS) devices, and the emergence of alternative nanotechnology devices, reliability challenges are of growing importance. Understanding and controlling the fault mechanisms associated with new materials and structures for both transistors and interconnection is a key issue in novel nanodevices. The graphene nanoribbon field-effect transistor (GNR FET) has revealed itself as a promising technology to design emerging research logic circuits, because of its outstanding potential speed and power properties. This work presents a study of fault causes, mechanisms, and models at the device level, as well as their impact on logic circuits based on GNR FETs. From a literature review of fault causes and mechanisms, fault propagation was analyzed, and fault models were derived for device and logic circuit levels. This study may be helpful for the prevention of faults in the design process of graphene nanodevices. In addition, it can help in the design and evaluation of defect- and fault-tolerant nanoarchitectures based on graphene circuits. Results are compared with other emerging devices, such as carbon nanotube (CNT) FET and nanowire (NW) FET. es_ES
dc.description.sponsorship This work was supported in part by the Spanish Government under the research project TIN2016-81075-R and by Primeros Proyectos de Investigacion (PAID-06-18), Vicerrectorado de Investigacion, Innovacion y Transferencia de la Universitat Politecnica de Valencia (UPV), under the project 200190032. es_ES
dc.language Inglés es_ES
dc.publisher MDPI AG es_ES
dc.relation.ispartof Electronics es_ES
dc.rights Reconocimiento (by) es_ES
dc.subject Emerging nanodevices es_ES
dc.subject Graphene nanoribbon FET es_ES
dc.subject Defects and variations es_ES
dc.subject Fault models es_ES
dc.subject Logic circuits es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.title Fault Modeling of Graphene Nanoribbon FET Logic Circuits es_ES
dc.type Artículo es_ES
dc.identifier.doi 10.3390/electronics8080851 es_ES
dc.relation.projectID info:eu-repo/grantAgreement/UPV//200190032/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/UPV//PAID-06-18/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/MINECO//TIN2016-81075-R/ES/MECANISMOS DE ADAPTACION CONFIABLE PARA VEHICULOS AUTONOMOS Y CONECTADOS/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/UPV//SP20180334/ es_ES
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.description.bibliographicCitation Gil Tomás, DA.; Gracia-Morán, J.; Saiz-Adalid, L.; Gil, P. (2019). Fault Modeling of Graphene Nanoribbon FET Logic Circuits. Electronics. 8(8):1-18. https://doi.org/10.3390/electronics8080851 es_ES
dc.description.accrualMethod S es_ES
dc.relation.publisherversion https://doi.org/10.3390/electronics8080851 es_ES
dc.description.upvformatpinicio 1 es_ES
dc.description.upvformatpfin 18 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 8 es_ES
dc.description.issue 8 es_ES
dc.identifier.eissn 2079-9292 es_ES
dc.relation.pasarela S\398479 es_ES
dc.contributor.funder Universitat Politècnica de València es_ES
dc.contributor.funder Ministerio de Economía y Competitividad es_ES
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