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dc.contributor.author | Valls Coquillat, Javier | es_ES |
dc.contributor.author | Torres Carot, Vicente | es_ES |
dc.contributor.author | Canet Subiela, Mª José | es_ES |
dc.contributor.author | García-Herrero, Francisco M. | es_ES |
dc.date.accessioned | 2020-12-17T04:33:40Z | |
dc.date.available | 2020-12-17T04:33:40Z | |
dc.date.issued | 2019-06 | es_ES |
dc.identifier.issn | 1549-8328 | es_ES |
dc.identifier.uri | http://hdl.handle.net/10251/157302 | |
dc.description | © 2019 IEEE. Personal use of this material is permitted. Permissíon from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertisíng or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | es_ES |
dc.description.abstract | [EN] This paper presents a low-complexity chase (LCC) decoder for Reed-Solomon (RS) codes, which uses a novel method for the selection of test vectors that is based on the analysis of the symbol error probabilities derived from simulations. Our results show that the same performance as the classical LCC is achieved with a lower number of test vectors. For example, the amount of test vectors is reduced by half and by 1/16 for the RS(255,239) and RS(255,129) codes, respectively. We provide an evidence that the proposed method is suitable for RS codes with different rates and Galois fields. In order to demonstrate that the proposed method results in a reduction of the complexity of the decoder, we also present a hardware architecture for an RS(255,239) decoder that uses 16 test vectors. This decoder achieves a coding gain of 0.56 dB at the frame error rate that is equal to 10(-6) compared with hard-decision decoding, which is higher than that of an eta = 5 LCC. The implementation results in ASIC show that a throughput of 3.6 Gb/s can be reached in a 90-nm process and 29.1XORs are required. The implementation results in Virtex-7 FPGA devices show that the decoder reaches 2.5 Gb/s and requires 5085 LUTs. | es_ES |
dc.description.sponsorship | This work was supported by the Spanish Ministerio de Economia y Competitividad and FEDER under Grant TEC2015-70858-C2-2-R. This paper was recommended by Associate Editor M. Boukadoum. | es_ES |
dc.language | Inglés | es_ES |
dc.publisher | Institute of Electrical and Electronics Engineers | es_ES |
dc.relation.ispartof | IEEE Transactions on Circuits and Systems I Regular Papers | es_ES |
dc.rights | Reserva de todos los derechos | es_ES |
dc.subject | Reed-Solomon | es_ES |
dc.subject | Algebraic soft-decision | es_ES |
dc.subject | Low-complexity chase | es_ES |
dc.subject | Error correction | es_ES |
dc.subject.classification | TECNOLOGIA ELECTRONICA | es_ES |
dc.title | A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding | es_ES |
dc.type | Artículo | es_ES |
dc.identifier.doi | 10.1109/TCSI.2018.2882876 | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/MINECO//TEC2015-70858-C2-2-R/ES/TRATAMIENTO DIGITAL DE LA SEÑAL Y CORRECCION DE ERRORES EN TRANSMISION OPTICA MEDIANTE FIBRA MULTI-NUCLEO PARA REDES OPTICAS DE ACCESO Y DE TRANSPORTE CELULAR/ | es_ES |
dc.rights.accessRights | Abierto | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica | es_ES |
dc.description.bibliographicCitation | Valls Coquillat, J.; Torres Carot, V.; Canet Subiela, MJ.; García-Herrero, FM. (2019). A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding. IEEE Transactions on Circuits and Systems I Regular Papers. 66(6):2198-2207. https://doi.org/10.1109/TCSI.2018.2882876 | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.publisherversion | https://doi.org/10.1109/TCSI.2018.2882876 | es_ES |
dc.description.upvformatpinicio | 2198 | es_ES |
dc.description.upvformatpfin | 2207 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.description.volume | 66 | es_ES |
dc.description.issue | 6 | es_ES |
dc.relation.pasarela | S\374692 | es_ES |
dc.contributor.funder | European Regional Development Fund | es_ES |
dc.contributor.funder | Ministerio de Economía y Competitividad | es_ES |