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A hierarchical architecture for time- and event-triggered real-time systems

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A hierarchical architecture for time- and event-triggered real-time systems

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dc.contributor.author Real Sáez, Jorge Vicente es_ES
dc.contributor.author Sáez Barona, Sergio es_ES
dc.contributor.author Crespo, Alfons es_ES
dc.date.accessioned 2021-01-14T04:32:19Z
dc.date.available 2021-01-14T04:32:19Z
dc.date.issued 2019-12 es_ES
dc.identifier.issn 1383-7621 es_ES
dc.identifier.uri http://hdl.handle.net/10251/158938
dc.description.abstract [EN] This paper proposes an architecture for combining the execution of time- and event-triggered real-time task sets. This makes it possible for the designer to choose the most appropriate mechanism depending on the role and nature of each task in the system. The proposed architecture allows one to choose the priority levels at which time- and event-triggered tasks are executed. This gives the designer an additional degree of freedom to make compromise decisions upon contradicting timing requirements, such as granting reduced jitter and at the same time providing prompt service to non-periodic events, for example. The proposed model is accompanied with a Ravenscar implementation of the time-triggered scheduler and a library of utilities for specifying time-triggered schedules and reusing time-triggered task patterns. es_ES
dc.description.sponsorship This work has been partly supported by Spanish Government and FEDER funds (AEI/FEDER, UE) under grant (TIN2017-86520-C3-1-R) (PRECON-I4); and by European Commission project AQUAS (ECSEL-JU, Contract 737475). es_ES
dc.language Inglés es_ES
dc.publisher Elsevier es_ES
dc.relation.ispartof Journal of Systems Architecture es_ES
dc.rights Reconocimiento - No comercial - Sin obra derivada (by-nc-nd) es_ES
dc.subject Real-time systems es_ES
dc.subject Time-triggered scheduling es_ES
dc.subject Ravenscar tasking profile es_ES
dc.subject High-integrity systems es_ES
dc.subject Embedded systems es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.title A hierarchical architecture for time- and event-triggered real-time systems es_ES
dc.type Artículo es_ES
dc.identifier.doi 10.1016/j.sysarc.2019.101652 es_ES
dc.relation.projectID info:eu-repo/grantAgreement/EC/H2020/737475/EU/Aggregated Quality Assurance for Systems/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2013-2016/TIN2017-86520-C3-1-R/ES/SISTEMAS INFORMATICOS PREDECIBLES Y CONFIABLES PARA LA INDUSTRIA 4.0/ es_ES
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.description.bibliographicCitation Real Sáez, JV.; Sáez Barona, S.; Crespo, A. (2019). A hierarchical architecture for time- and event-triggered real-time systems. Journal of Systems Architecture. 101:1-15. https://doi.org/10.1016/j.sysarc.2019.101652 es_ES
dc.description.accrualMethod S es_ES
dc.relation.publisherversion https://doi.org/10.1016/j.sysarc.2019.101652 es_ES
dc.description.upvformatpinicio 1 es_ES
dc.description.upvformatpfin 15 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 101 es_ES
dc.relation.pasarela S\397704 es_ES
dc.contributor.funder European Commission es_ES
dc.contributor.funder Agencia Estatal de Investigación es_ES
dc.contributor.funder European Regional Development Fund es_ES


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