- -

Locality-aware cache random replacement policies

RiuNet: Repositorio Institucional de la Universidad Politécnica de Valencia

Compartir/Enviar a

Citas

Estadísticas

  • Estadisticas de Uso

Locality-aware cache random replacement policies

Mostrar el registro sencillo del ítem

Ficheros en el ítem

dc.contributor.author Benedicte, Pedro es_ES
dc.contributor.author Hernández Luz, Carles es_ES
dc.contributor.author Abella, Jaume es_ES
dc.contributor.author Cazorla, Francisco J. es_ES
dc.date.accessioned 2021-02-06T04:33:41Z
dc.date.available 2021-02-06T04:33:41Z
dc.date.issued 2019-02 es_ES
dc.identifier.issn 1383-7621 es_ES
dc.identifier.uri http://hdl.handle.net/10251/160830
dc.description.abstract [EN] Measurement-Based Probabilistic Timing Analysis (MBPTA) facilitates the analysis of complex software running on hardware comprising high-performance features. MBPTA also aims at preventing additional analysis costs for timing analysis techniques and preserving the confidence on derived WCET estimates. Cache behavior has a deep influence on WCET estimates and hence on "the amount of software" that can be consolidated onto a single hardware platform. Deterministic replacement policies such as LRU (Least Recently Used) and NMRU (Non-Most Recently Used) have systematic pathological cases that may lead to high execution times and WCET estimates. Instead, random replacement (RR) decreases pathological cases probability, at the cost of temporal locality. We present two new MBPTA-amenable replacement policies that completely remove the presented pathological cases. The first policy, Random Permutations (RP) preserves higher temporal locality than RR; while the second, NMRU Random Permutations (NMRURP), also protects the Most Recently Used line from eviction. Both proposed policies build upon restricted random replacement choices. Our simulation evaluation (validated against a real prototype) using the Malardalen benchmarks and a case study shows that RP and NMRURP deliver both high average performance (within 1% of LRUs and NRMU performance) and tight WCET estimates 11% and 24% lower than those of RR. es_ES
dc.description.sponsorship This work has been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under grant TIN2015-65316-P, the European Research Council (ERC) under the European Union's Horizon 2020 research and innovation programme (grant agreement No. 772773) and the HiPEACH Network of Excellence. Pedro Benedicte and Jaume Abella have been partially supported by the MINECO under FPU15/01394 grant and Ramon y Cajal postdoctoral fellowship number RYC-2013-14717 respectively. es_ES
dc.language Inglés es_ES
dc.publisher Elsevier es_ES
dc.relation.ispartof Journal of Systems Architecture es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject WCET es_ES
dc.subject Cache memory es_ES
dc.subject Replacement policy es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.title Locality-aware cache random replacement policies es_ES
dc.type Artículo es_ES
dc.identifier.doi 10.1016/j.sysarc.2018.12.007 es_ES
dc.relation.projectID info:eu-repo/grantAgreement/EC/H2020/772773/EU/Sustainable Performance for High-Performance Embedded Computing Systems/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/MINECO//RYC-2013-14717/ES/RYC-2013-14717/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/MINECO//TIN2015-65316-P/ES/COMPUTACION DE ALTAS PRESTACIONES VII/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/MECD//FPU15%2F01394/ES/FPU15%2F01394/ es_ES
dc.rights.accessRights Cerrado es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.description.bibliographicCitation Benedicte, P.; Hernández Luz, C.; Abella, J.; Cazorla, FJ. (2019). Locality-aware cache random replacement policies. Journal of Systems Architecture. 93:48-61. https://doi.org/10.1016/j.sysarc.2018.12.007 es_ES
dc.description.accrualMethod S es_ES
dc.relation.publisherversion https://doi.org/10.1016/j.sysarc.2018.12.007 es_ES
dc.description.upvformatpinicio 48 es_ES
dc.description.upvformatpfin 61 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 93 es_ES
dc.relation.pasarela S\393380 es_ES
dc.contributor.funder European Commission es_ES
dc.contributor.funder HiPEAC Network of Excellence es_ES
dc.contributor.funder Ministerio de Economía y Competitividad es_ES
dc.contributor.funder Ministerio de Educación, Cultura y Deporte es_ES
dc.description.references Wilhelm, R., Engblom, J., Ermedahl, A., Holsti, N., Thesing, S., Whalley, D., … Stenström, P. (2008). The worst-case execution-time problem—overview of methods and survey of tools. ACM Transactions on Embedded Computing Systems, 7(3), 1-53. doi:10.1145/1347375.1347389 es_ES
dc.description.references Abella, J., Padilla, M., Castillo, J. D., & Cazorla, F. J. (2017). Measurement-Based Worst-Case Execution Time Estimation Using the Coefficient of Variation. ACM Transactions on Design Automation of Electronic Systems, 22(4), 1-29. doi:10.1145/3065924 es_ES
dc.description.references COBHAM, LEON3 Processor. Probabilistic platform, (http://www.gaisler.com/ index.php/products/processors/leon3). es_ES
dc.description.references Esterel Technologies, SA, Efficient Developement of Safe Avionics Software with DO-178B Objectives Using SCADE Suite - Methodological Handbook, 2006. es_ES
dc.description.references International Organization for Standardization, ISO/DIS 26262. Road Vehicles – Functional Safety, 2009. es_ES
dc.description.references International Electrotechnical Comission, IEC 61508, Functional Safety of Electrical/Electronic/Programmable Electronic Safety-related Systems, Edition 2.0, 2009. es_ES
dc.description.references Kosmidis, L., Quiñones, E., Abella, J., Vardanega, T., Hernandez, C., Gianarro, A., … Cazorla, F. J. (2016). Fitting processor architectures for measurement-based probabilistic timing analysis. Microprocessors and Microsystems, 47, 287-302. doi:10.1016/j.micpro.2016.07.014 es_ES
dc.description.references SoCLib, 2003–2012, http://www.soclib.fr/trac/dev. es_ES
dc.description.references Karedla, R., Love, J. S., & Wherry, B. G. (1994). Caching strategies to improve disk system performance. Computer, 27(3), 38-46. doi:10.1109/2.268884 es_ES
dc.description.references Belady, L. A. (1966). A study of replacement algorithms for a virtual-storage computer. IBM Systems Journal, 5(2), 78-101. doi:10.1147/sj.52.0078 es_ES
dc.description.references ARM, Cortex-R4 and Cortex-R4F Technical Reference Manual, 2006. es_ES


Este ítem aparece en la(s) siguiente(s) colección(ones)

Mostrar el registro sencillo del ítem