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Simulation-Based Analysis on Operational Control of Batch Processors in Wafer Fabrication

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Simulation-Based Analysis on Operational Control of Batch Processors in Wafer Fabrication

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dc.contributor.author Koo, Pyung-Hoi es_ES
dc.contributor.author Ruiz García, Rubén es_ES
dc.date.accessioned 2021-05-12T03:32:12Z
dc.date.available 2021-05-12T03:32:12Z
dc.date.issued 2020-09 es_ES
dc.identifier.uri http://hdl.handle.net/10251/166214
dc.description.abstract [EN] In semiconductor wafer fabrication (wafer fab), wafers go through hundreds of process steps on a variety of processing machines for electrical circuit building operations. One of the special features in the wafer fabs is that there exist batch processors (BPs) where several wafer lots are processed at the same time as a batch. The batch processors have a significant influence on system performance because the repetitive batching and de-batching activities in a reentrant product flow system lead to non-smooth product flows with high variability. Existing research on the BP control problems has mostly focused on the local performance, such as waiting time at the BP stations. This paper attempts to examine how much BP control policies affect the system-wide behavior of the wafer fabs. A simulation model is constructed with which experiments are performed to analyze the performance of BP control rules under various production environments. Some meaningful insights on BP control decisions are identified through simulation results. es_ES
dc.description.sponsorship This work was supported by the Pukyong National University Research Abroad Fund (C-D-2016-0843). es_ES
dc.language Inglés es_ES
dc.publisher MDPI AG es_ES
dc.relation.ispartof Applied Sciences es_ES
dc.rights Reconocimiento (by) es_ES
dc.subject Batch processors es_ES
dc.subject Real-time control es_ES
dc.subject Dispatching es_ES
dc.subject Wafer fabrication es_ES
dc.subject Semiconductor manufacturing es_ES
dc.subject System-wide performance es_ES
dc.subject.classification ESTADISTICA E INVESTIGACION OPERATIVA es_ES
dc.title Simulation-Based Analysis on Operational Control of Batch Processors in Wafer Fabrication es_ES
dc.type Artículo es_ES
dc.identifier.doi 10.3390/app10175936 es_ES
dc.relation.projectID info:eu-repo/grantAgreement/PKNU//C-D-2016-0843/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/RTI2018-094940-B-I00/ES/OPTIMIZACION DE OPERACIONES EN TERMINALES PORTUARIAS/ es_ES
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Estadística e Investigación Operativa Aplicadas y Calidad - Departament d'Estadística i Investigació Operativa Aplicades i Qualitat es_ES
dc.description.bibliographicCitation Koo, P.; Ruiz García, R. (2020). Simulation-Based Analysis on Operational Control of Batch Processors in Wafer Fabrication. Applied Sciences. 10(17):1-17. https://doi.org/10.3390/app10175936 es_ES
dc.description.accrualMethod S es_ES
dc.relation.publisherversion https://doi.org/10.3390/app10175936 es_ES
dc.description.upvformatpinicio 1 es_ES
dc.description.upvformatpfin 17 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 10 es_ES
dc.description.issue 17 es_ES
dc.identifier.eissn 2076-3417 es_ES
dc.relation.pasarela S\424886 es_ES
dc.contributor.funder Pukyong National University es_ES
dc.contributor.funder Agencia Estatal de Investigación es_ES
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