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Phase-Aware Cache Partitioning to Target Both Turnaround Time and System Performance

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Phase-Aware Cache Partitioning to Target Both Turnaround Time and System Performance

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Pons-Escat, L.; Sahuquillo Borrás, J.; Selfa, V.; Petit Martí, SV.; Pons Terol, J. (2020). Phase-Aware Cache Partitioning to Target Both Turnaround Time and System Performance. IEEE Transactions on Parallel and Distributed Systems. 31(11):2556-2568. https://doi.org/10.1109/TPDS.2020.2996031

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/168885

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Title: Phase-Aware Cache Partitioning to Target Both Turnaround Time and System Performance
Author: Pons-Escat, Lucía Sahuquillo Borrás, Julio Selfa, Vicent Petit Martí, Salvador Vicente Pons Terol, Julio
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Issued date:
Abstract:
[EN] The Last Level Cache (LLC) plays a key role in the system performance of current multi-cores by reducing the number of long latency main memory accesses. The inter-application interference at this shared resource, ...[+]
Subjects: System performance , Interference , Throughput , Measurement , Heuristic algorithms , Program processors , Multicore processing , Cache memories , Multi-core multiprocessors , Memory structures , Memory hierarchy , Performance
Copyrigths: Reserva de todos los derechos
Source:
IEEE Transactions on Parallel and Distributed Systems. (issn: 1045-9219 )
DOI: 10.1109/TPDS.2020.2996031
Publisher:
Institute of Electrical and Electronics Engineers
Publisher version: https://doi.org/10.1109/TPDS.2020.2996031
Project ID:
info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/RTI2018-098156-B-C51/ES/TECNOLOGIAS INNOVADORAS DE PROCESADORES, ACELERADORES Y REDES, PARA CENTROS DE DATOS Y COMPUTACION DE ALTAS PRESTACIONES/
GVA/AICO/2019/317
Description: © 2020 IEEE. Personal use of this material is permitted. Permissíon from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertisíng or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Thanks:
This work has been supported in part by Ministerio de Ciencia, Innovaci~on y Universidades and the European ERDF under Grant RTI2018-098156-B-C51, and Generalitat Valenciana under Grant AICO/2019/317.
Type: Artículo

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