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Hardware design of computer arithmetic blocks for engineering laboratory practices

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Hardware design of computer arithmetic blocks for engineering laboratory practices

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dc.contributor.author Vázquez, J. es_ES
dc.contributor.author Carrasco, R. es_ES
dc.contributor.author Ortegón, J. es_ES
dc.contributor.author Castillo, A. es_ES
dc.contributor.author ROCHA GASO, MARÍA ISABEL es_ES
dc.contributor.author Cabañas, V. es_ES
dc.date.accessioned 2023-03-22T19:00:47Z
dc.date.available 2023-03-22T19:00:47Z
dc.date.issued 2018-06 es_ES
dc.identifier.uri http://hdl.handle.net/10251/192551
dc.description.abstract [EN] This work presents a set of laboratory experiments that can be carried out by students who are taking digital design courses in engineering programs like Electronics, Communications Systems and Mechatronics. The purpose of these labs is to help students develop their skills and confidence designing arithmetic hardware blocks through solving of specific problems. In this aspect, this paper shows a method to be followed in the laboratory to design arithmetic blocks and implement them in microcontrollers and FPGAs. More specifically, the block design of a number's multiplicative inverse (1/root x), its square root (root x) and the square root of its inverse (1/root x) are presented. To complete these exercises, knowledges on Newton-Raphson algorithm, difference equations and digital design are required. Students of our institution completed the lab practices, and after analyzing the results from student surveys and classroom observations, we found out that completing these tasks significantly contributed to the students' training in the hardware design field. es_ES
dc.description.sponsorship Este trabajo fue financiado por el Consejo Nacional de Ciencia y Tecnología (CONACYT) de México, mediante el proyecto de Ciencia Básica número 241272 es_ES
dc.language Inglés es_ES
dc.publisher Institute of Electrical and Electronics Engineers es_ES
dc.relation.ispartof IEEE Latin America Transactions es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject Computing arithmetic es_ES
dc.subject Hardware design es_ES
dc.subject Laboratory practices es_ES
dc.subject Digital design es_ES
dc.subject Engineering es_ES
dc.subject.classification TECNOLOGIA ELECTRONICA es_ES
dc.title Hardware design of computer arithmetic blocks for engineering laboratory practices es_ES
dc.type Artículo es_ES
dc.identifier.doi 10.1109/TLA.2018.8444156 es_ES
dc.relation.projectID info:eu-repo/grantAgreement/CONACYT//241272/ es_ES
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Escuela Técnica Superior de Ingeniería del Diseño - Escola Tècnica Superior d'Enginyeria del Disseny es_ES
dc.description.bibliographicCitation Vázquez, J.; Carrasco, R.; Ortegón, J.; Castillo, A.; Rocha Gaso, MI.; Cabañas, V. (2018). Hardware design of computer arithmetic blocks for engineering laboratory practices. IEEE Latin America Transactions. 16(6):1610-1615. https://doi.org/10.1109/TLA.2018.8444156 es_ES
dc.description.accrualMethod S es_ES
dc.relation.publisherversion https://doi.org/10.1109/TLA.2018.8444156 es_ES
dc.description.upvformatpinicio 1610 es_ES
dc.description.upvformatpfin 1615 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 16 es_ES
dc.description.issue 6 es_ES
dc.identifier.eissn 1548-0992 es_ES
dc.relation.pasarela S\482507 es_ES
dc.contributor.funder Consejo Nacional de Ciencia y Tecnología, México es_ES


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