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dc.contributor.author | Rodríguez-Agut, David | es_ES |
dc.contributor.author | Tornero-Gavilá, Rafael | es_ES |
dc.contributor.author | Flich Cardo, José | es_ES |
dc.date.accessioned | 2024-03-05T12:03:11Z | |
dc.date.available | 2024-03-05T12:03:11Z | |
dc.date.issued | 2023-04-19 | es_ES |
dc.identifier.isbn | 978-3-9819263-7-8 | es_ES |
dc.identifier.issn | 1938-1891 | es_ES |
dc.identifier.uri | http://hdl.handle.net/10251/202929 | |
dc.description.abstract | [EN] Nowadays, convolutional neural networks (CNN) are common in a wide range of applications. Their high accuracy and efficiency contrast with their computing requirements, leading to the search for efficient hardware platforms. FPGAs are suitable due to their flexibility, energy efficiency and low latency. However, the ever increasing complexity of CNNs demands higher capacity devices, forcing the need for multi-FPGA platforms. In this paper, we present a multi-FPGA platform with distributed shared memory support for the inference of CNNs. Our solution, in contrast with previous works, enables combining different model parallelism strategies applied to CNNs, thanks to the distributed shared memory support. For a four FPGA setting, the platform reduces the execution time of 2D convolutions by a factor of 3.95 when compared to single FPGA. The inference of standard CNN models is improved by factors ranging 3.63-3.87. | es_ES |
dc.language | Inglés | es_ES |
dc.publisher | IEEE | es_ES |
dc.relation.ispartof | 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) | es_ES |
dc.rights | Reserva de todos los derechos | es_ES |
dc.subject | Multi-FPGA | es_ES |
dc.subject | Neural Networks | es_ES |
dc.subject | Deep Learning | es_ES |
dc.subject.classification | ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES | es_ES |
dc.title | Towards Efficient Neural Network Model Parallelism on Multi-FPGA Platforms | es_ES |
dc.type | Comunicación en congreso | es_ES |
dc.type | Artículo | es_ES |
dc.type | Capítulo de libro | es_ES |
dc.identifier.doi | 10.23919/DATE56975.2023.10137117 | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/EC/H2020/955558/EU | es_ES |
dc.rights.accessRights | Abierto | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Escola Tècnica Superior d'Enginyeria Informàtica | es_ES |
dc.description.bibliographicCitation | Rodríguez-Agut, D.; Tornero-Gavilá, R.; Flich Cardo, J. (2023). Towards Efficient Neural Network Model Parallelism on Multi-FPGA Platforms. IEEE. 1-6. https://doi.org/10.23919/DATE56975.2023.10137117 | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.conferencename | Design, Automation and Test in Europe Conference (DATE 2023) | es_ES |
dc.relation.conferencedate | Abril 17-19,2023 | es_ES |
dc.relation.conferenceplace | Antwerp, Belgium | es_ES |
dc.relation.publisherversion | https://doi.org/10.23919/DATE56975.2023.10137117 | es_ES |
dc.description.upvformatpinicio | 1 | es_ES |
dc.description.upvformatpfin | 6 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.relation.pasarela | S\496674 | es_ES |