- -

Cost-effective queue schemes for reducing head-of-line blocking in fat-trees

RiuNet: Repositorio Institucional de la Universidad Politécnica de Valencia

Compartir/Enviar a

Citas

Estadísticas

  • Estadisticas de Uso

Cost-effective queue schemes for reducing head-of-line blocking in fat-trees

Mostrar el registro completo del ítem

Escudero, J.; García García, PJ.; Quiles Flor, FJ.; Flich Cardo, J.; Duato Marín, JF. (2011). Cost-effective queue schemes for reducing head-of-line blocking in fat-trees. Concurrency and Computation: Practice and Experience. 23(17):2235-2248. https://doi.org/10.1002/cpe.1764

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/30495

Ficheros en el ítem

Metadatos del ítem

Título: Cost-effective queue schemes for reducing head-of-line blocking in fat-trees
Autor: Escudero, Jesús García García, Pedro Javier Quiles Flor, Francisco Jose Flich Cardo, José Duato Marín, José Francisco
Entidad UPV: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Fecha difusión:
Resumen:
The fat-tree is one of the most common topologies among the interconnection networks of the systems currently used for high-performance parallel computing. Among other advantages, fat-trees allow the use of simple but very ...[+]
Palabras clave: Interconnection networks , Fat-trees , Deterministic routing , Head-of-line blocking
Derechos de uso: Cerrado
Fuente:
Concurrency and Computation: Practice and Experience. (issn: 1532-0626 )
DOI: 10.1002/cpe.1764
Editorial:
Wiley-Blackwell
Versión del editor: http://onlinelibrary.wiley.com/doi/10.1002/cpe.1764/pdf
Código del Proyecto:
info:eu-repo/grantAgreement/MEC//CSD2006-00046/ES/Arquitecturas fiables y de altas prestaciones para centros de proceso de datos y servidores de Internet/
...[+]
info:eu-repo/grantAgreement/MEC//CSD2006-00046/ES/Arquitecturas fiables y de altas prestaciones para centros de proceso de datos y servidores de Internet/
info:eu-repo/grantAgreement/MICINN//TIN2009-14475-C04-01/ES/Arquitecturas De Servidores, Aplicaciones Y Servicios/
info:eu-repo/grantAgreement/MICINN//TIN2009-14475-C04-03/ES/Arquitecturas De Servidores, Aplicaciones Y Servicios/
info:eu-repo/grantAgreement/Junta de Comunidades de Castilla-La Mancha//PCC08-0078-9856/ES/Técnicas eficientes de encaminamiento y calidad de servicio en redes en chip/
info:eu-repo/grantAgreement/Junta de Comunidades de Castilla-La Mancha//POII10-0289-3724/ES/Mejora de la calidad de servicio ofrecida por la infraestructura de Internet/
info:eu-repo/grantAgreement/Junta de Comunidades de Castilla-La Mancha//A08%2F048/ES/A08%2F048/
[-]
Agradecimientos:
This work is jointly supported by the MEC, MICINN and European Commission under projects Consolider Ingenio-2010-CSD2006-00046 and TIN2009-14475-C04, and by the Junta de Comunidades de Castilla-La Mancha under projects ...[+]
Tipo: Artículo

References

Myrinet, 2000 Series Networking http://www.myri.com/myrinet/

http://www.infinibandta.com/

Top 500 List http://www.top500.org [+]
Myrinet, 2000 Series Networking http://www.myri.com/myrinet/

http://www.infinibandta.com/

Top 500 List http://www.top500.org

Leiserson, C. E. (1985). Fat-trees: Universal networks for hardware-efficient supercomputing. IEEE Transactions on Computers, C-34(10), 892-901. doi:10.1109/tc.1985.6312192

Gomez C Gilabert F Gomez M Lopez P Duato J Deterministic versus adaptive routing in fat-trees 2007 235

Karol, M., Hluchyj, M., & Morgan, S. (1987). Input Versus Output Queueing on a Space-Division Packet Switch. IEEE Transactions on Communications, 35(12), 1347-1356. doi:10.1109/tcom.1987.1096719

Dally W Carvey P Dennison L Architecture of the Avici terabit switch/router 41 50

Anderson, T. E., Owicki, S. S., Saxe, J. B., & Thacker, C. P. (1993). High-speed switch scheduling for local-area networks. ACM Transactions on Computer Systems, 11(4), 319-352. doi:10.1145/161541.161736

Tamir, Y., & Frazier, G. L. (1992). Dynamically-allocated multi-queue buffers for VLSI communication switches. IEEE Transactions on Computers, 41(6), 725-737. doi:10.1109/12.144624

Nachiondo, T., Flich, J., & Duato, J. (2010). Buffer Management Strategies to Reduce HoL Blocking. IEEE Transactions on Parallel and Distributed Systems, 21(6), 739-753. doi:10.1109/tpds.2009.63

Garcia, P. J., Quiles, F. J., Flich, J., Duato, J., Johnson, I., & Naven, F. (2006). Efficient, Scalable Congestion Management for Interconnection Networks. IEEE Micro, 26(5), 52-66. doi:10.1109/mm.2006.88

Mora G García PJ Flich J Duato J RECN-IQ: A cost-effective input-queued switch architecture with congestion management

Escudero-Sahuquillo J García PJ Quiles FJ Flich J Duato J FBICM: Efficient congestion management for high-performance networks using distributed deterministic routing 2008 503 517

Escudero-Sahuquillo, J., Garcia, P. J., Quiles, F. J., & Duato, J. (2010). An Efficient Strategy for Reducing Head-of-Line Blocking in Fat-Trees. Lecture Notes in Computer Science, 413-427. doi:10.1007/978-3-642-15291-7_39

Leiserson, C. E., & Maggs, B. M. (1988). Communication-efficient parallel algorithms for distributed random-access machines. Algorithmica, 3(1-4), 53-77. doi:10.1007/bf01762110

Petrini F Vanneschi M k -ary n -trees: High performance networks for massively parallel architectures 87 93

Gomez ME Lopez P Duato J A memory-effective routing strategy for regular interconnection networks

Dongarra J http://www.netlib.org/benchmark/performance.ps

Ridruejo, F. J., Gonzalez, A., & Miguel-Alonso, J. (s. f.). TrGen: A Traffic Generation System for Interconnection Network Simulators. 2005 International Conference on Parallel Processing Workshops (ICPPW’05). doi:10.1109/icppw.2005.86

Thoziyoor S Muralimanohar N Ahn JH Jouppi NP Cacti 5.1. Technical Report hpl-2008-20 2008

[-]

recommendations

 

Este ítem aparece en la(s) siguiente(s) colección(ones)

Mostrar el registro completo del ítem